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Issue 1, 2013
Verdi3™ - The Industry’s Open Debug Platform
Thomas Li, product marketing director, Synopsys, explains how the open architecture of the Verdi3™ system enables design and verification teams to accelerate their innovation by providing them with a fully integrated, predictable environment including out-of-the-box support for a wide range of leading simulators, emulators, FPGA-prototyping solutions, model checkers, formal analysis engines and virtual platforms.
The problems that verification teams face today are well documented. Typically, approximately 70% of a project’s resources can be absorbed in the verification process, and half of the verification cycles are dedicated to debugging the design.
In order to tackle rising design complexity, verification teams must choose the best verification tools for the job. Increasingly, they assemble heterogeneous flows, comprising RTL and gate-level simulation, system-level verification and prototyping environments, and emulation hardware. They mix and match tools from different vendors, selecting the tools that offer better performance at a particular abstraction level or offer other features that enable them to verify faster.
Verification teams sometimes choose the best combination of simulator engines to suit their particular design style. For example, Synopsys VCS® is a popular choice for RTL simulation in conjunction with other popular gate-level simulators. The verification team may be using a variety of simulation technologies across different parts of the design for historical reasons. Company acquisitions often bring a number of engineering teams together, with each team having access to different legacy simulators. Aligning the entire team to use a new simulator can be disruptive and require extensive retraining.
While heterogeneous verification environments bring together the best engines to tackle the complete design at different stages of the project, using these engines to actually debug the design can be challenging. Typically each engine will have a different user interface, different ways of displaying waveforms, and different features available for debug. Often, debug is so tightly coupled with the simulator it is serving that it’s impossible to use the same debug with a different engine. Engineers have to adapt to using the different interfaces and come up with ways of analyzing a variety of waveform databases. These limitations can severely inhibit debug productivity.
Verdi3 Automated Debug System
Verdi3 provides teams with a unified debugging solution for use across the entire heterogeneous verification environment. It supports a broad range of methodologies and languages used to design and verify complex SoCs. Its open architecture enables teams to use a single display format, sophisticated feature set, and unified waveform database whether they are using simulation engines from the same EDA supplier or different vendors.
Verdi3’s open architecture is the key to providing a more productive debug environment, which enables verification teams to literally cut their debug times in half. According to a Synopsys customer survey, verification teams reported a 50% reduction in debug time as a result of deploying Verdi3. Building Verdi3 on an open architecture allows verification teams to customize and personalize the environment to suit their verification processes and maximize productivity.
By providing an automated environment that integrates tools and flows within a flexible, efficient architecture, Verdi3 enables verification teams to understand and debug their designs faster and more effectively (Figure 1).
Figure 1: Verdi3 automated debug system
Verdi3 incorporates several key features that help to enable efficient debugging within heterogeneous simulation environments.
Efficient Waveform Compression and Analysis
The Fast Signal Database (FSDB) is fundamental to the open nature of Verdi3. It works on all leading simulators, emulators, and many other verification tools. It is completely open to all EDA vendors, as well as customers, for both reading and writing. The FSDB offers superior waveform compression compared to many waveform databases, and it works independently of the simulator engine version. It enables verification engineers to load multiple waveforms so that they can compare them easily.
Verdi Interoperable Apps (VIA) enable verification teams to easily customize their debug solutions to maximize productivity (Figure 2). VIA supports simple access to the design database through the use of scripts or C/C++ programs, which allows verification teams to automate features that are specific to their verification process or application. For example, engineers can easily perform design pattern filtering on the design database or sweep the FSDB to search for a particular waveform to perform accurate power estimation. Engineers can launch VIA-enabled third-party tools from the debug environment and access a rich array of VIA programs to tailor Verdi3 deployment for user flows.
Application programming interfaces (APIs) provide open access to both databases and command-and-control mechanisms, enabling verification teams to easily integrate the Verdi3 system with other verification tools and design environments.
Figure 2: VIA programming interface enables flow integration and customization
Opening Up Design Knowledge
The Verdi3 system is built on the open Design Knowledge Architecture. It consists of compilers that extract relevant information into databases, which are optimized for efficient debug. The Design Knowledge Architecture includes knowledge engine compilers that extract design knowledge contained in HDL code, testbenches and assertions. The knowledge database (KDB) stores design knowledge to facilitate debug and design understanding.
Behavior-based debugging provides the intelligence behind the debug capabilities of Verdi3. By combining knowledge of the design structure from the compiled databases with the simulation waveform results (FSDB), Verdi3 saves design teams hours of time by automating behavior tracing.
The Verdi3 debug environment will even work on incomplete designs; they are highly fault tolerant. The benefit for design engineers is that they can load the design into Verdi3 in order to begin to understand the structure of the design before it is complete. This enables engineers to more easily get up to speed with new, unfamiliar IP, for example.
As well as the advanced debugging capabilities described above, the Verdi3 system supports all of the debug features that verification teams expect from a capable debug environment. There is a full-featured waveform viewer, waveform comparison engine, source code browser that enables engineers to easily traverse between source code and hierarchy, flexible schematics and block diagrams that display logic and connectivity using familiar symbols (Figure 3), and intuitive bubble diagrams that help reveal the operation of finite state machines.
Figure 3: The unique behavior analysis technology of the Verdi3 system automates many time-consuming aspects of debug
Third-Generation Open Architecture Debug
Verdi3 is designed with the sole purpose of improving debug productivity for design and verification teams. This release of the automated debug platform improves on previous versions by providing a faster, smaller and more efficient infrastructure. The multi-threaded database improves performance by more than 45%, file sizes shrink by more than 30% thanks to the new compact database format, and the ability to dump simulations in parallel boosts productivity by another 30%.
Alongside these efficiency improvements, Verdi3 introduces more flexibility for verification engineers to personalize their user interfaces to suit their particular debug needs. In addition, VIA integration provides a rich set of programs to tailor the debug environment to the needs of the team’s flow.
The successful deployment of Verdi3 is attributable to its open architecture. Design and verification teams are able to accelerate their innovative designs since they are able to cut their debug times in half – or more – after adopting Verdi3, even when using heterogeneous verification environments.
About the Author
Thomas Li is Product Marketing Director at Synopsys, responsible for the company’s debug solutions. He has over 17 years of EDA industry experience, having held technical positions in product marketing, applications engineering and design services consulting. Thomas joined Synopsys through the acquisition of SpringSoft where he was the product marketing director for the Verdi product line. He has a M.S. degree in Computer Science & Information Engineering from National Chung-Cheng University, Taiwan, and an MBA from Saint Mary’s College, California.