Synopsys Insight Newsletter 

Insight Home   |  Previous Article   |   Next Article

Issue 1, 2012

Technology Update
Discovery: A New Generation of Verification IP

Verification intellectual property (IP) has shown its worth over recent years as a vital component in enhancing SoC verification productivity. Neill Mullinger, Synopsys, explains the company’s new approach to verification IP: Discovery™ VIP.

Consumer demand for faster, higher-definition, longer-lasting electronic products is continually driving the development of more efficient, more complex, communications interfaces. The new USB 3.0 protocol, for example, offers 10x the performance of its predecessors. Because interfaces are based almost exclusively on standards like MIPI, USB, PCI Express®, SATA, OCP, etc, IP providers can offer interface IP to design teams “off the shelf” allowing them to focus their engineering resources on the value-added parts of their products. As communications standards continue to rapidly evolve, buying IP rather than investing to develop expertise for in-house development is proving to be of significant benefit to engineering teams.

But it is a somewhat different story for verification teams. They require significant expertise for the interface protocols they are testing in order to produce a test plan, develop tests, configure the VIP, debug the protocol and identify gaps in coverage. Developing verification IP is time-consuming and requires expert knowledge of the protocol. Even when using a third-party vendor’s IP, it takes a deep understanding of the protocol to use it effectively and to interpret what is happening to the traffic at the interface.

Changing the Nature of Verification IP
Most of today’s commercial VIP is based on a mish-mash of interconnected languages and methodologies. There is typically a base model developed using languages like C, e, or OpenVera that provides the underlying protocol behavior. Then, translation wrappers enable design teams to use the VIP in different languages and methodologies of the testbench such as SV, UVM, VMM or OVM. Supporting multiple languages and methodologies can often result in multiple layers and the need to call secondary simulation engines for the underlying VIP. This layered approach creates limitations in both performance and methodology.

Discovery VIP
We have been re-focusing our approach to verification IP over the past couple of years to address the performance bottlenecks described above, as well as improving the ease-of-use and portability of our verification IP. This has culminated in the release of Discovery VIP, a new generation of VIP.

At the core of Discovery VIP is an architecture that is based 100% on SystemVerilog and has been developed to run native UVM, VMM or OVM using best practices for those methodologies. The methodology is chosen at compile time and only the chosen methodology’s class library is used. This removes the need for wrapping or layers between the underlying VIP and the methodology the verification team is using in the testbench and delivers the best of both worlds: excellent performance and full methodology support. Around this SystemVerilog core, we have developed a number of features and applications that are closely linked into the architecture to increase overall productivity through four major aspects of protocol-based verification (Figure 1):
  • Rapid Configuration and Test
  • High Performance
  • Easier Debug
  • Quick Coverage Closure

Figure 1
Figure 1: New verification IP vision

Rapid Configuration and Test
This first part is all about getting to first test quickly. It involves ramping on the VIP, instantiating it, configuring it, developing a test plan, and writing the first test. This can be time consuming and quite daunting when using a VIP for the first time. To accelerate this aspect, we have included a new configuration tool that guides users through the process of configuring the VIP to match the interface being tested. A test plan provides a comprehensive list of cover points for the protocol with references back to the specification. Changes to the configuration will modify the built-in coverage reporting from the VIP so only the relevant cover data is included in the plan and the results. QuickStart documentation provides a task-based view of using the VIP that focuses on the key steps in getting the VIP instantiated, configured, initialized and running, which gives new users in particular a fast ramp on building their environment.

High Performance
High Performance is enabled by the 100% SystemVerilog implementation running natively on the simulator of choice without the need for wrappers or Direct Programming Interfaces (DPIs). Profiling tools have been used with the code to eliminate bottlenecks and deliver the highest performance. Performance benefits have been seen of up to 4x compared to other wrapped VIP. All simulators are inherently supported and tested.

Easier Debug
Another advantage of the 100% SystemVerilog architecture is that debug becomes much simpler. There is no need to be familiar with a different language in the underlying VIP; it is all SystemVerilog, and there are no wrappers to peel through to find the root cause of problems. In addition, the new and innovative Protocol Analyzer tool provides a new protocol-aware debug environment that raises the level of abstraction of the protocol and unravels the interleaving (Figure 2). This makes it easy to track the activity on the interface and view the hierarchical relationships between transfers, transactions, data packets and handshaking.

Figure 2
Figure 2: Protocol Analyzer display of AMBA® 4 AXI4™ and USB 3.0 verification

Quick Coverage Closure
We are reducing time to coverage by building the coverage reporting into the Discovery VIP. Coverage data can be back annotated into the test plan to track progress and identify coverage holes. The test plan and coverage can both be modified and extended by the users to target application specific tests.

A protocol-based sequence library is included to provide stimulus to accelerate coverage of the protocol. This saves the expertise and time of having to write tests and constraints from scratch. Like coverage, the sequences are modified by the configuration of the VIP.

Boosting Productivity
The complexity and pervasiveness of today’s standard interfaces demands a different approach to verification if verification teams are to meet increasingly aggressive project timescales.

By delivering a completely new verification IP environment, we are enabling verification engineers to improve their productivity over an expanding number of protocols.


More Information:

About the Author
Neill Mullinger is a group marketing manager at Synopsys. In this role he focuses on verification IP and methodology support and has product manager responsibility for Synopsys DesignWare® Verification IP. Neill joined Synopsys in 2000 and has over 20 years experience in the hardware and EDA industries, bringing an extensive background of verification experience to bear on product and methodology definition.


Having read this article, will you take a moment to let us know how informative the article was to you.
Exceptionally informative (I emailed the article to a friend)
Very informative
Informative
Somewhat informative
Not at all informative