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Issue 4, 2012
Using Advances in Synthesis Technology to Cut Implementation Time
Small-geometry effects can undermine design productivity and offset the integration benefits of systems-on-chip—unless these effects are accounted for during RTL synthesis. Stacy Frank, staff design engineer with Integrated Device Technology (IDT), and Chris Allsup, marketing manager in Synopsys' synthesis and test group, discuss how physical guidance and other innovations in Design Compiler Graphical have minimized design iterations and cut implementation time at IDT. This article originally appeared in the winter 2012 issue of Chip Design, pages 22-26.
Over the past decade, advances in both semiconductor process technologies and design implementation solutions have enabled the development of highly integrated systems-on-chip (SoCs) that have fueled dramatic growth in portable consumer electronic appliances worldwide. Recently, however, a new challenge has emerged that threatens to undermine design productivity and offset the integration benefits of SoCs. At 65 nanometers (nm) and below, a combination of longer wire lengths and reduced spacing between wires has increased interconnect coupling capacitance to such an extent that it significantly affects design timing.
Increased coupling capacitance has given rise to a marked decrease in correlation between synthesis results and layout results—an issue that makes it more challenging than ever before to synthesize a design with demanding quality-of-results (QoR) for timing, area and power that carry through to physical implementation. Uncorrelated results necessitate numerous, time-consuming iterations between synthesis, floorplanning and place-and-route (P&R) to meet strict timing, area and power goals across multiple corners and operating modes of a design.
To improve correlation, Integrated Device Technology (IDT), a developer of complex application-optimized mixed-signal ICs for timing, serial switching and interfaces, has used new synthesis technologies as part of the development of its Tsi721 PCIe2 to S-RIO2 protocol conversion bridge. This device is an ~16-million-gate SoC that converts PCIe Gen2 at 20 Gbaud rate to RapidIO 2, also at 20 Gbaud, and vice versa. Inside the device, there are 8 channels for DMA and messaging, each of which can keep up with the full line rate of 20 Gbaud at 64 byte packets or greater. Using the new synthesis technologies discussed in this article, IDT was able to reduce iterations and decrease the time and resources needed to meet IDT's challenging design goals, which was to bring the world's first PCIe2 to S-RIO2 SoC device to market, with first-pass success. Before discussing these new technologies, let's take a closer look at the impact uncorrelated results have on SoC design implementation time.
Impact of Uncorrelated Results
Design iterations caused by uncorrelated QoR are resource intensive and pose a significant risk to tapeout schedules. Figure 1 compares design implementation times for two example scenarios involving a hypothetical 65-nm SoC project: the first assumes nominal correlation of timing, area and power between synthesis and layout, and the second assumes high correlation. The individual time slices represent the time spent performing synthesis and P&R. For brevity, the verification tasks are not shown.
In the first scenario, a substantial amount of implementation time and effort is needed to achieve design closure. After initial synthesis by the front-end design team, all timing, area and power goals apparently have been met, so the netlist is passed to the back-end design team. After placement is completed, timing violations reveal a divergence of QoR between synthesis and layout: the design's timing goals have not been met after all, and this requires changes to the RTL, physical constraints or both. Once these changes have been made, the design is re-synthesized and placement performed again. At this stage, timing violations again indicate that synthesis QoR has not carried through to the layout. The iterations continue in this manner until timing closure is finally achieved and all the design goals are met.
Figure 1: High correlation between synthesis and layout reduces design iterations
and decreases design implementation time.
In the second scenario, the synthesis and layout results are highly correlated so that only one pass is needed to achieve design closure. Reducing the number of design iterations results in a major reduction in implementation time and effort for a project. Let's see how this is accomplished.
Passing Physical Guidance to Placement
To begin with, facilitating timing-driven placement optimization in synthesis is critical. In Design Compiler Graphical, Synopsys has increased delay modeling accuracy in its topographical technology by accounting for coupling capacitance and cell density in addition to wire lengths—a necessity for designs fabricated at 65 nm and below. More accurate interconnect delay modeling improves timing accuracy and helps identify design issues early in the flow.
Achieving much better placement optimization also means that these results can be used to create a better starting point for the physical implementation phase of design. Passing physical guidance to IC Compiler for seed placement makes it possible to achieve very strong correlation between synthesis and layout, enabling not only fewer design iterations but faster placement runtimes.
Extensive evaluation yielded some very interesting results. Figure 2 displays scatter plots comparing synthesis delays with post-optimized placement delays for a block that has particularly challenging timing requirements. The plot on the left reflects baseline results with a large number of delays falling outside the ±5% range without physical guidance technology. In contrast, the plot on the right side reflects results obtained using physical guidance technology in synthesis, and we see that most of the delays fall within the ±5% range. These results confirmed our expectations that highly correlated placement would translate into highly correlated timing results.
Moreover, both worst negative slack (WNS) and total negative slack (TNS) of the post-optimized placement timing with physical guidance improved over the baseline case by 27% and 37%, respectively. This demonstrates that better QoR for the post-placement results is a natural byproduct of synthesis' passing physical guidance to placement to create a better starting point for physical implementation.
Figure 2: Passing Synopsys physical guidance from Design Compiler Graphical to IC Compiler
leads to highly correlated timing paths.
Instant Access to Floorplanning
While Figure 1 highlighted the synthesis-P&R iterations, it did not call attention to the synthesis-floorplan iterations that often occur during each synthesis step. Synthesis often reveals design issues such as timing violations and routing congestion that require changes to the floorplan. In a traditional flow, depicted in the top scenario of Figure 3, the design is passed to the back-end design team, which then makes the needed adjustments to the floorplan. The design is then passed back to the front-end design team for re-synthesis based on the new floorplan constraints. This process continues until the synthesis QoR goals are met. These iterations can also occur during the synthesis phase of subsequent synthesis-P&R iterations. For example, a routing congestion issue could surface during P&R that requires RTL changes and re-synthesis.
Figure 3: Access to floorplanning from inside synthesis reduces the impact synthesis-floorplanning
iterations have on design implementation time.
Because all the back-and-forth handoffs between front-end and back-end design teams incur extra delay, another way to improve SoC design productivity is to provide instant access to floorplan creation and modification from inside the Design Compiler environment. This approach, shown as the bottom scenario of Figure 3, avoids the inefficiencies involved with synthesis-floorplanning handoffs and leads to faster convergence to an optimal floorplan. With pushbutton access to floorplanning, RTL designers can easily explore a range of floorplan options and fix any issues from within synthesis, thereby creating a better starting point for physical implementation. In addition, routing congestion prediction and mitigation capabilities make it easy to identify potential congestion hot spots—whether caused by the floorplan or by highly interconnected logic structures in the netlist—and perform targeted optimizations to remove the congestion before the handoff to P&R. This further reduces the number of synthesis-P&R iterations.
Aggressive SoC design goals for 65 nm and below must be met in a timely manner that makes the most efficient use of IDT's design resources. To accomplish this, it is essential that the synthesis solution achieve excellent QoR and preserve these results downstream in the physical implementation flow. By creating a better starting point for physical implementation, Synopsys' Design Compiler Graphical with physical guidance enables highly correlated results between synthesis and P&R, leading to better design timing and up to 2x faster placement. Deploying the new synthesis technologies at IDT has minimized design iterations, helping us mitigate project risk and meet design goals in shorter timeframes.
About the Authors
Stacy Frank is a staff design engineer with Integrated Device Technology working with the Ottawa Design Center (formerly Tundra Semiconductor). Her responsibilities include synthesis & timing constraints, formal verification and Static Timing Analysis. She has a BS in Electrical Engineering from the University of Southern Maine in Gorham, Maine and began her career working for Quadic Systems, a small design center that was acquired by Tundra Semiconductor back in 2000.
Chris Allsup, marketing manager in Synopsys' synthesis and test group, has more than 20 years combined experience in IC design, field applications, sales, and marketing. He earned a BSEE degree from UC San Diego and an MBA degree from Santa Clara University. Chris is a member of IEEE Computer Society and has authored numerous articles and papers on design and test.