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Issue 4, 2012
Ace the Verification of Multicore SoCs
Chris Thompson, staff applications consultant at Synopsys, explains in his latest white paper how using the right verification IP (VIP) can help engineers to quickly and efficiently verify complex multicore systems that incorporate cache coherency based on the ARM® AMBA® 4 ACE™ protocol.
The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. Traditionally, design teams implemented cache control protocols in software. Today, hardware implementation of cache coherency is the preferred option for those design teams looking for better performance and lower power. ARM is moving toward the use of hardware for cache control by introducing the AMBA 4 ACE (AXI Coherency Extensions) protocol.
While the use of hardware to implement cache coherency enables design teams to improve system-on-chip (SoC) performance, it adds significantly to verification complexity. The use of VIP enables engineers to validate such designs, although the VIP's effectiveness depends on the extent of its support for the AMBA ACE protocol.
- Verifying Cache Coherency Protocols with Verification IP
The white paper explains:
- The key cache coherency challenges
- How cache coherency works with a bus-based shared-memory approach
- What cache coherency protocols do
- ARM's cache coherency model
- The ACE protocol cache state model
- The principles that design teams must follow when using the ACE protocol
- Memory barriers and distributed virtual memory
- The impact on verification of multicore SoCs
Synopsys’ SystemVerilog-based VIP suite and Reference Verification Platform (RVP) provides comprehensive support for ACE protocol cache coherency, which enables design teams to accelerate the verification of complex multicore SoCs that take advantage of this protocol. The verification suite provides native support for UVM, VMM, and OVM methodologies, and includes comprehensive support for generating stimulus sequences as well as automatic built-in checks, coverage and debug capabilities. It enables design teams to automatically create representations of their systems with VIP using a configurable top-level template, using configurable components such as those shown in Figure 1.
Figure 1: Synopsys Discovery VIP for AMBA AXI and ACE Protocols
Synopsys' white paper will help designers to better understand the operation of ARM's AMBA 4 ACE cache coherency protocol and select VIP that improves the predictability of their verification processes.
Synopsys' Discovery VIP for AMBA 4 AXI and ACE protocols provides a 100% SystemVerilog-based VIP suite that supports the full protocol, including IP interconnect, and is easy to configure from a system-level environment.
A reference verification platform, such as Synopsys' RVP, which is built using Synopsys' SystemVerilog-based Discovery VIP suite, can help design teams to quickly and efficiently verify multicore systems that incorporate cache coherency control.
Download the full white paper
About the Author
Chris Thompson is a staff applications consultant at Synopsys with 20 years of experience specializing in SystemVerilog functional verification using advanced methodologies (VMM, UVM) as well as verification IP (VIP). Prior to joining Synopsys, Thompson worked as an ASIC verification consultant both for Qualis and independently, as well as an ASIC verification engineer at several telecom and semiconductor companies. Chris holds a B.ASc. in electrical engineering from the University of Ottawa, Canada.