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Issue 3, 2013

Customer Highlight
Common Sense: New IP Subsystem Reduces Design Risk for SoC Sensor Integration

Rich Collins, product marketing manager for IP Subsystems at Synopsys, explains how Synopsys’ new DesignWare® Sensor IP subsystem is optimized to process data from digital and analog sensors, enabling ultra-low power processing of the sensor data while freeing up the host processor.

Common Sense: New IP Subsystem Reduces Design Risk for SoC Sensor Integration In the past, sensor technology has often been associated with industrial and military applications, commonly used for process monitoring and control. Today, sensors are increasingly being used to revolutionize electronic products so that people can utilize them in more versatile, simple and intelligent ways within consumer products, communications, cars, security systems, medical systems and many other applications.

Sensor Market Soars
Many innovative and differentiated applications, such as those found in mobile devices, rely on sensors’ abilities to interpret environmental conditions such as pressure, temperature, motion and proximity. As a result, sensors are becoming much more sophisticated and prevalent. Semico Research is predicting double-digit growth for sensor shipments over the next few years (Figure 1).

Common Sense: New IP Subsystem Reduces Design Risk for SoC Sensor Integration
Figure 1: Sensor shipments to grow to 30 billion units in 2017

“The total number of sensor units is estimated to grow from just under 10 billion in 2012 to nearly 30 billion in 2017,” said Tony Massimini, chief of technology at Semico Research. “As more semiconductor suppliers integrate sensor interfaces into their System-on-Chips (SoCs), the use of sensor IP subsystems such as Synopsys’ DesignWare Sensor IP Subsystem will significantly reduce their integration effort and cost.”

Sensor Fusion Drives Integration and Processing
While the sheer number of sensors in electronics systems increases, so does the processing requirement for sensor data. The rise in sophistication of sensor technology is leading design teams to implement sensor fusion techniques to intelligently combine data from multiple sensors in order to improve information accuracy and product functionality.

For example, a smartphone may combine data from a gyroscope, e-compass, accelerometer and pressure sensor in order to calculate elevation, linear translation, gravity, direction and rotation. The device can combine this information to derive 3D rotation and translation, which it can then use to control screen rotation, inform gesture recognition, gaming, step counting and personal navigation. This higher level of sensor functionality increases the complexity of the sensor system and requires more processing performance.

The complexity of building a sensor fusion system is compounded by the need to integrate more functionality onto a single SoC. To achieve this goal, designers are looking for ways to move away from discrete ICs and toward integrated sensor control within their SoCs without burdening the SoC’s application processor. One architectural approach is to integrate standalone IP blocks for SoC-based sensor control. However, this shifts the burden to the design team to independently verify and debug this “home grown” system, which is both time consuming and susceptible to error.

As these sensor systems become more complex, design teams are increasingly looking for complete IP subsystems, consisting of pre-integrated, verified hardware and software that they can quickly integrate with less risk, enabling them to focus their efforts on the differentiated portions of their design.

Interfacing SoC Sensors
Many design teams treat sensor interfaces as standard peripheral devices when integrating them into their SoC designs. A typical architecture consists of a shared bus that connects on-chip memories, peripherals and sensor interfaces to the CPU (Figure 2). With latency and traffic, transactions across the bus typically take three to seven clock cycles, which adversely affects performance and power consumption. The DesignWare Sensor IP Subsystem offers designers an alternative low-power, high-performance approach to implementing SoC-sensor interfaces by pre-integrating sensor-specific IP blocks together with an efficient processor and software into a single solution.

Common Sense: New IP Subsystem Reduces Design Risk for SoC Sensor Integration
Figure 2: How design teams commonly implement sensors today using discrete components

Integrated, Pre-Verified DesignWare Sensor IP Subsystem
Synopsys optimized its DesignWare Sensor IP Subsystem to process digital and analog sensor data. The configurable subsystem features a power- and area-efficient DesignWare ARC® EM4 32-bit processor, which includes custom extensions and instructions that support application-specific hardware accelerators and tightly integrated peripherals. In addition, the subsystem includes multiple configurable GPIO, SPI and I2C digital interfaces for off-chip sensor connections as well as ARM® AMBA® AHB™/APB™ protocol system interfaces to ease subsystem integration into the full SoC. The analog-to-digital data converter (ADC) interfaces efficiently digitize analog sensor data for the processor.

The software portions of the Sensor IP Subsystem provide extensive support for DSP functions which include complex mathematical, filtering (FIR, IIR, correlation, etc.), matrix/vector and decimation/interpolation operations. These functions help accelerate sensor application code development and can be implemented in software, hardware or both to reduce memory footprint and decrease power consumption. Peripheral software drivers are provided to ease integration of the I/O with the ARC EM4 processor, and host drivers are provided to interface the DesignWare Sensor IP Subsystem to the host processor.

By using the Sensor IP Subsystem, design teams can create more efficient sensor-based architectures, which reduce on-chip area, latency and power consumption (Figure 3). The integrated architecture offers a number of benefits over traditional bus-based architectures:

Closely Coupled Memories (I-CCM, D-CCM)
The DesignWare ARC EM4 processor core enables designers to integrate tightly coupled memories for both instructions and data, which reduces access times going across the AHB bus to ROM and RAM in a bus-based topology.

Tightly Integrated I/O
The ARC processor implementation can eliminate the interface to on-chip buses by replacing load/store instructions to the I/O peripheral with register move instructions. The peripheral block registers are mapped using the ARC processor’s auxiliary bus.

The architecture pulls the I/O peripheral interface functionality into the CPU complex, eliminating buses and bridges. Tightly coupling the I/O in this manner enables single cycle access to all peripheral functions, improving performance and reducing power consumption, while reducing die area due to the use of fewer gates.

Customizable Hardware and Custom Instructions
Design teams using ARC processors can add any combination of hardware extensions to the core: CPU extension registers, auxiliary extension registers, or memory mapped blocks, as well as 32-bit custom instructions. The hardware extensions are added with standard code (either as Verilog or C) and are accessed and run using custom-defined instructions.

Common Sense: New IP Subsystem Reduces Design Risk for SoC Sensor Integration
Figure 3: High-level sensor IP subsystem based on the ARC EM4 processor

Proven Results
Figure 4 demonstrates that significant chip area savings are possible across a wide range of use cases when using a DesignWare Sensor IP Subsystem compared with a traditional sensor implementation. A typical Sensor IP Subsystem implementation can yield area savings of 40% to 60% compared to normal bus-based implementations. The Sensor IP Subsystem architecture also reduces the memory footprint and power consumption by a factor of 10 when compared to implementations that use discrete IP components.

Common Sense: New IP Subsystem Reduces Design Risk for SoC Sensor Integration
Figure 4: Traditional implementations normalized to DesignWare Sensor IP Subsystem implementations for common sensor control applications

Customer View
“As the technology leader in magnetic sensor ICs for the automotive market, it is critical that Allegro acquires high-quality IP from a trusted provider such as Synopsys. Based on our experience, the DesignWare ARC 32-bit processor’s combination of high performance, small area and low power provides key advantages for sensor design over alternative solutions.”

Robert Fortin, director of sensors business unit at Allegro Microsystems, LLC.


More Information

About the Author
Rich Collins is the product marketing manager for IP Subsystems at Synopsys. In this role, he is responsible for developing strategies and positioning for market penetration and growth of ARC processors and ARC-based subsystems within the DesignWare IP portfolio. Mr. Collins is an industry veteran with over 20 years of experience in embedded semiconductor R&D, product marketing and business development. Before joining Synopsys, he spent 17 years at Motorola/Freescale, where he held several technical and managerial roles within CPU, IP and SoC design and marketing teams across the company. Mr. Collins holds an MBA from Duke University's Fuqua School of Business as well as a BSE in Electrical Engineering from Duke University, where he also majored in Computer Science and Spanish.


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