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Issue 4, 2011
Building Low-Power, High-Performance Mobile SoCs with Complete MIPI Solutions
Consumers continually expect more from mobile electronics. Hezi Saar, marketing manager responsible for the MIPI IP portfolio at Synopsys, lifts the lid on how the MIPI Alliance is helping to keep pace with the latest trends in the mobile market.
Mobile Market Trends
In the past decade, we moved from focusing on electronics for home or computing to mobile devices. We have compact mobile devices that do much more than the PCs of yesteryear, allowing us to access information on the go. Today's abundance of applications running on multiple platforms offers a variety of practical uses in our daily lives.
Consumers continuously demand more features and functions from their mobile electronics: faster connections, high resolution displays, multiple image sensors and rapidly increasing data transfers. With more functions converged into a single device, it's becoming extremely challenging for SoC designs to keep up with the exploding bandwidth, advanced integration functionality and low power constraints.
Standardizing the Mobile Industry
How is this demand for added features and flexibility being addressed?
The Mobile Industry Processor Interface (MIPI) Alliance establishes specifications for hardware and software interfaces in mobile devices. Its specifications focus on eliminating proprietary, legacy, often point-to-point or parallel interfaces, while improving interoperability and reducing power consumption, pin-count and integration costs. The MIPI Alliance offers a wide range of chip-to-chip interfaces that are "inside the mobile device", as opposed to external interfaces such as HDMI and USB.
The MIPI Alliance has over 200 members (and growing), including key vendors to the mobile industry and strong contributors like Synopsys, who participate in many working groups and co-author some of the specifications. The members define and promote interfaces that drive consistency in processor and peripheral interfaces, promote reuse and compatibility in mobile devices and facilitate product innovation.
Figure 1: Connectivity enabled by MIPI specifications
Figure 1 shows major components often found in a mobile device such as a smartphone and many MIPI interfaces that help connect these components together. MIPI specifications enable multiple chip-to-chip interfaces serving different purposes. On the application processor side, interfaces for display, camera, storage and high-speed communication are found. On the baseband processor side, there are high-speed connectivity and baseband-to-RFIC interfaces.
Market momentum for MIPI interfaces is strong. IPNest indicates that almost all worldwide IC shipments in handsets will be using MIPI interfaces by 2013. Analysts from InStat and iSupply project strong adoption of MIPI camera (CSI-2) and display (DSI) interfaces in mobile electronics including mobile computing applications such as tablets.
There are many applications utilizing MIPI-enabled standard connectivity. Mobile multimedia and wireless connectivity devices are the natural fit for mobile interfaces that enable standard chip-to-chip connectivity and higher scalability while minimizing power. It is likely that there will also be penetration of MIPI-enabled interfaces in home, computing, industrial and even telematics applications utilizing the low power and low system cost profile of the MIPI specifications and their wide adoption.
Popular MIPI Protocols
The mobile market demands high performance, low power and scalable interfaces to enable manufacturers to easily upgrade their mobile device platforms and avoid costly re-design.
Figure 2 below shows some of the most popular MIPI Alliance interfaces used in the market today. They enable connectivity between baseband and application processors to RFICs, image sensors and display ICs, and offer the benefits of scalability, lower power, improved reliability and lower system cost.
Figure 2: Today's most popular MIPI interfaces
- There are a number of MIPI display and camera specifications that enable standard connectivity to the application processor:
- Display serial interface (DSI): Allows standard, efficient and low power connectivity between the application processor and display that is embedded in the mobile device. More information
- Camera serial interface (CSI-2): An efficient low power, low pin-count interface that connects the image sensor to the application processor. The CSI-2 protocol provides the functional means to transfer the data between the devices, including detecting and correcting errors that may occur during transmission. A separate I2C-compliant interface is used for camera control interface (CCI) functions. The CSI-2 interface supports a variety of data and color space formats, transfer in packets, lane management, error detection and correction. More information
- D-PHY: Serves as the electrical and physical connection allowing the implementation of the CSI-2 or DSI protocol between the application processor to the display or image sensor. It provides a high-performance serial differential interface offering up to four data lanes, plus a common differential clock lane meeting the need to connect to multi-megapixel cameras and high resolution displays to the application processor. More information
To see system-level interoperability in action using Synopsys' DesignWare® MIPI CSI-2, DSI host controller and D-PHY IP solution, see the 'Synopsys Demonstrates MIPI Camera and Display Prototyping System' video.
Next-Generation MIPI Protocols
The next-generation MIPI protocols will be used as the foundation of several mobile applications to support the needs for higher resolution and increased bandwidth, utilizing the M-PHY physical layer. The most common use of the M-PHY physical layer today is with the DigRFv4 controller, which is used to communicate with the standard baseband RFIC. Design teams can also use the M-PHY physical layer to implement a number of other application-specific and application-agnostic protocols.
Figure 3: M-PHY-based MIPI protocols
M-PHY: The Foundation for Mobile Protocols
The M-PHY protocol uses differential signaling and an embedded clock in a dual simplex lane configuration, and provides a feature set that's optimized for a spectrum of mobile applications. More information
Since one of the most important criteria for the mobile industry is low power, the DesignWare MIPI M-PHY IP offers a variety of low power capabilities, including:
- Multiple low power states, to ease transition from high-speed burst to save states such as 'stall', 'sleep' and 'hibernate'
- Support for a variety of system-optimized power operation modes including low-speed, high-speed, and low-power:
- Low-speed mode for low-bandwidth operation
- High-speed mode for burst transmission, achieving lowest power per bit
- Low-power mode for low leakage and fast sleep/wakeup
- ON/OFF switched termination
- No Tx pre-emphasis and no Rx equalization
- Programmable amplitude
Achieving low electromagnetic interference (EMI) is extremely important in mobile electronics – the devices are small and their components closely packed, creating an environment that is very sensitive to RF signals. The M-PHY features help to lower EMI and reduce interference through:
- Low amplitude option
- Programmable slew rate
- Limited common mode noise
- Dual bandwidth rates A and B for each high-speed gear
Because the M-PHY interface supports a wide data bandwidth range, design teams can operate it in high-speed mode to avoid interference and reduce noise in the device, while achieving high performance and optimal low power system operation.
To see M-PHY silicon in action, view the video below which showcases large and small amplitude measurements taken from Synopsys' silicon proven DesignWare M-PHY.
Figure 4: Silicon-proven M-PHY video demonstration
As higher air traffic demand continues to increase, we see more 3G and 4G/LTE networks being deployed and supported by wireless carriers. As a result, more manufacturers are introducing 4G RFICs that support high bandwidth transfers. The typical non-standard implementation could use many pins to implement a 4G data connection from the baseband processor and RFIC, and does not provide the scalability needed for the breadth of mobile electronics flavors.
The MIPI DigRF specification defines a high-speed serial interface between RF transceiver ICs and baseband processors, meeting the increased data throughput requirements for mobile terminals. DigRFv4 is the latest specification targeting 4G standard air interfaces such as LTE and mobile WiMAX, as well as supporting existing 3G standards. It is a high-bandwidth standard interface that makes use of the scalable MIPI M-PHY to support existing and next generation mobile broadband requirements, simplifying system integration as well as reducing power, pin-count, EMI and overall cost.
LLI, SSIC, UFS, and CSI-3
Other application-specific M-PHY-based protocols include:
- Low-latency interface (LLI). The low-latency interface is primarily used for cache refill of a companion chip using the application processor attached memory. This means the interface based on the M-PHY, with multiple lanes in each direction, needs to be simple and scalable to achieve the latency-sensitive chip-to-chip implementation. There are other interesting use cases for this chip-to-chip capability such as connecting companion chips to an application processor or SoC, or transmitting data over non-proprietary but standard interfaces.
- SuperSpeed inter-chip (SSIC). The USB 3.0 promoters group signed a memorandum of understanding with the MIPI Alliance allowing the USB working group to develop this USB chip-to-chip protocol, a standard still under definition. This collaboration supports low power and high-speed implementations that allow reuse of the USB drivers to support the widely-used USB 3.0 standard interface. This highly flexible and reusable approach will allow chip-to-chip connectivity between host and peripherals.
UniPro, an application-agnostic protocol that is also based on M-PHY for the physical layer, supports the following applications:
- Universal flash storage (UFS): JEDEC signed a memorandum of understanding with the MIPI Alliance to develop this storage interface based on MIPI M-PHY and MIPI UniPro specifications. JEDEC aims for its UFS standard to be the storage interface in mobile and consumer electronics to enable effective storage and consumption of rich multimedia. The UFS standard is currently available and published by JEDEC.
- CSI-3, the next-generation camera interface, and DSI-2, the next-generation display interface (specifications are under definition). Display and imaging technologies like 3D and high-resolution continue to push the boundaries of bandwidth for image sensors and displays. CSI-3 and DSI-2 are targeting to meet these requirements and add to the capabilities of today's CSI-2 and DSI protocols that are based on D-PHY.
Figure 5: MIPI system-on-chip design example
Figure 5 shows a design that Synopsys developed internally for a typical application processor or SoC, implementing camera and display interfaces to demonstrate a complete, end-to-end video stream. The D-PHY, shown on the left of Figure 5, is connected to the image sensor that receives the captured image, and transmits it to the CSI-2 host controller. The controller unpacks the data, checks for errors and uses the bridge and simplified microprocessor implementation to send the image to the DSI host controller via the D-PHY to the external DSI display. This example demonstrates how a set of proven MIPI IP solutions can help design teams quickly and easily integrate critical functionality into their SoCs.
Synopsys and the MIPI Alliance
Synopsys has been an active contributor to the MIPI Alliance for many years and is also a part of USB Implementer Forum (USB-IF) and JEDEC standards organizations. We use the knowledge, expertise, and experience gained by being a member of the MIPI Alliance to develop high-quality IP solutions that are compliant with the latest MIPI specifications, enabling our customers to integrate these interfaces into their SoCs with less risk. Synopsys has done extensive testing of our MIPI IP solutions with camera, display and RFIC devices in the market to further reduce the risk associated with system-level interoperability.
About the Author
Hezi Saar serves as a staff product marketing manager at Synopsys and is responsible for its DesignWare MIPI controller and PHY IP product line. He brings more than 15 years of experience in the semiconductor and electronics industries in embedded systems. Prior to joining Synopsys, Saar was responsible for Advanced Interface IP at Virage Logic (which was acquired by Synopsys in September 2010). From 2004 to 2009, Saar served as senior product marketing manager leading Actel's Flash field-programmable-gate-array (FPGA) product lines. Previously, he served as a product marketing manager at ISD/Winbond and as a senior design engineer at RAD Data Communications. Saar holds a Bachelor of Science degree from Tel Aviv University in computer science and economics and an MBA from Columbia Southern University.