DesignWare Technical Bulletin  

What's New with DesignWare minPower Components 

DesignWare® minPower Components extend the capabilities of DesignWare IP to reduce the power consumption of energy sensitive applications. This technology focuses on reducing power for datapath-intensive designs. DesignWare minPower Components, originally released in 2009.06-SP1, have undergone several updates over the last year. These updates have added features that help to provide better quality-of-results (QoR) and maximize the power savings achieved (Power QoR) with DesignWare minPower Components.

Incremental Datapath Gating: Before retiming, the enable signals of the first stage retiming registers that initially placed at the outputs are identified as DG enable signals. After retiming, the first stage registers can be moved into a gated DesignWare block. When this happens, the input signals are already held steady by its driver registers when the DG enable signal is off. Therefore, DG can reduce the power before retiming, but not after retiming. So the Incremental Datapath Gating feature has been added to enhance the datapath gating for retiming flows and improving Power QoR. Below are the commands to enable the incremental datapath gating feature:

set power_enable_datapath_gating true
#The next command is only needed in two pass retiming flows
#and should be called prior to the first compile
set_datapath_gating_options -retime <instance_name>
-retime_clk_period <retime_clk_period>

minPower Components Block-Level Control: This feature provides the ability to control minPower Components at the block level, allowing the flexibility to indicate where minPower Components should focus its efforts in a design. With this feature, you can maximize power savings by identifying the datapath blocks that consume the most power and enable minPower Components only to those blocks.

#This command enables/disables minPower optimizations globally
set_dp_smartgen_options -power_effort off

#This command enables/disables minPower optimizations per instance
set_dp_smartgen_options -power_effort auto <instance_name>

minPower Components Optimization in Leakage Mode: Prior to 2010.12-SP4, the minPower leakage optimizations were only enabled in leakage mode. In 2010.12-SP4 and onward all minPower Components optimization are used in leakage mode, providing savings of both dynamic and leakage power.

Datpath Content Report: command has been added to report the datapath content percentage in your design. Below is the command to generate the datapath content reporting:

analyze_datapath

This command reports the percentage of the design composed of singletons, extracted datapath content and total datapath. It also includes a breakdown of the types of operators and their bit widths. This information can be useful, since a design with more than 20% datapath content, having adders, multipliers, shifters, subtractors and large bit width operators (≥ 8 bit) is more likely to benefit from minPower Components.

DesignWare Datapath Power Report: A new report has been added to better understand the power contribution of each datapath cell towards total dynamic and leakage power and total power contribution from all datapath cells. This helps identify the datapath blocks that are big power contributors and what kind of savings to expect at top level based on the total power contribution from these blocks. This report also details available timing slack information for the datapath cells in the design.

set synlib_enable_analyze_dw_power true
analyze_dw_power –hier

minPower Components Optimization Reports: To better understand the power optimizations performed by minPower Components, new options have been added to report_resources command.

report_resources –hier -minpower –context
-minpower #report datapath blocks that are optimized for power
-context #reports switching information on inputs of all datapath blocks

With more blocks optimized for power and higher switching activity provided on inputs of datapath blocks, you can expect to see more power savings from minPower Components.

Enhanced DG Reporting to Better Understand Gating Opportunities: The gating report was enhanced so that it is easier for you to understand gating opportunities in your design. This report provides a datapath gating summary and gives reasons why operators are not gated (if any)

compile_ultra
report_datapath_gating -ungated

It is recommended you use 2010.12-SP5 or later DC versions to fully utilize all the latest features added to minPower Components.

New Instantiable minPower Components: DesignWare minPower Components also includes instantiable IP with low power features. Many of these components are related to DesignWare Building Block IP that perform the same function, but the minPower Components’ implementations apply low power strategies to save power, while providing the same functionality. The following describe some of the new instantiable components:

DW_lp_multifunc_DG
DW_lp_fp_multifunc_DG –Floating-Point version

Low power multifunctional math unit. Summary of features:
  • Seven functions
    math unit
  • Supports any combination of the above seven functions
  • Built in support for automatic datapath gating to provide power savings

For detailed information on this new component, please visit here.

DW_lp_piped_fp_add

Low power pipelined floating point adder. Internal pipeline manager saves power by intelligently enabling or disabling register stages. Summary of features:
  • Saves power by only enabling stages as needed
  • Saves power based on input data patterns
  • Parameter controlled pipeline stages
  • Flow control to interface directly to FIFO
  • Flow control interfaces to another managed pipe
  • Bubble removal extends depth of subsequent FIFO by pipe depth

For detailed information on this new component, please visit here.

DW_lp_cntr_up_df

General-purpose counter with dynamic "count-to" logic reduces power consumption through efficient clock gating. Summary of features:
  • Parameter-controlled counter width
  • Dynamically controlled terminal count flag specification
  • Parameter-controlled selection of registered flag output
  • Parameter-controlled selection of Synchronous versus Asynchronous reset
  • Synchronous Enable
  • Synchronous Load

For detailed information on this new component, please visit here.

DW_lp_cntr_updn_df

General-purpose up/down counter with dynamic "count-to" logic reduces power consumption through efficient clock gating. Summary of features:
  • Parameter-controlled counter width
  • Dynamically controlled terminal count flag specification
  • Parameter-controlled selection of registered flag output
  • Parameter-controlled selection of Synchronous versus Asynchronous reset
  • Synchronous Enable
  • Synchronous Load

For detailed information on this new component, please visit here.

DW_lp_fifoctl_1c_df

Fully configurable FIFO controller solution accommodates a wide variety of synchronous RAM architectures and includes features that are designed to alleviate timing issues in both the push_n and pop_n interfaces. Summary of features:
  • RAM read enable control
  • Alternative caching architectures
  • RTL implementations that minimize power consumption

In addition to the components described above, new floating point components supporting datapath gating have also been added. The table below highlights these new components:

ComponentDatasheet link
DW_fp_addsub_DG https://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_addsub_DG.pdf
DW_fp_add_DG https://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_add_DG.pdf
DW_fp_sub_DG https://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_sub_DG.pdf
DW_fp_mult_DG https://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_mult_DG.pdf
DW_fp_mac_DG https://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_mac_DG.pdf
DW_fp_cmp_DG https://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_cmp_DG.pdf
DW_fp_sum3_DGhttps://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_sum3_DG.pdf
DW_fp_div_DG https://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_div_DG.pdf
DW_fp_recip_DG https://www.synopsys.com/dw/doc.php/doc/dwmp/datasheets/DW_fp_recip_DG.pdf

Enhanced DesignWare Building Block IP: The following DesignWare Building Block (DWBB) IP has been updated with minPower Component implementations. The new low power implementations of these blocks will automatically be selected in place of the standard DWBB part if the minPower Component license (DesignWare-LP) is available.

For more information on the DesignWare minPower Components, please visit here



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