July 18, 2012 – On the morning of June 13, 2012, hundreds of Synopsys users arrived at the ITC Gardenia hotel in Bangalore, India to learn from each other and discuss the best ways to tackle some of today's greatest design challenges. Hosting more than 2,100 attendees, SNUG India has become one of the largest, most important SNUG events worldwide. The two-day conference, held from June 13 to 14, included two keynote speeches, three vision sessions, nine tutorials, 44 user papers, an 'Ask the Experts' panel on best practices for high-performance processor core implementation, the fourth PrimeTime SIG event, and an impressive Designer Community Expo.
"SNUG India has grown to record attendance numbers because the program showcases Synopsys technologies through customer case studies and presentations. It's not enough to just talk about the latest technology offerings. Engineers want to hear what other users are actually doing with the tools," said Manjunath Haritsa, Synopsys director of application consulting based in India. "I heard from one user this year who decided to deploy a new tool for his designs after seeing another user's presentation at SNUG India. An example like this is powerful because it demonstrates how users can learn from each other to tackle their greatest design challenges."
Mr.Haritsa opened this year's SNUG India with a welcome address that also introduced keynote speaker Deirdre Hanford, senior vice president of Global Technical Services at Synopsys. Ms. Hanford delivered a standing-room-only, high energy keynote speech entitled, "Innovation – Continuing to Push the Boundaries of What's Possible." During her talk, she walked through some of Synopsys' latest innovations and wove in information from a few key customer papers. Aloknath De, CTO of Samsung India Software Operation Pvt. Ltd, offered additional technology insights during his keynote on day two called, "What Makes a Smart Device Smart—an SoC Design Perspective."
- In addition to the customer papers, the Synopsys team presented tutorials in seven technical tracks:
- Custom Design and AMS Verification
- IC Design: Signoff
- IC Design: Test and FPGA
- IC Design: Implementation
- IC Design: Low Power
- IC Verification
- Systems and IP
More than 500 users attended the Designer Community Expo (DCE), taking time to meet with representatives from Synopsys and its design community partners. The DCE gave users the opportunity to network with other engineers and browse the 30 featured booths across seven designer communities while enjoying food, drinks and prizes.
Presenters at the Prime Time SIG event, chaired by Jagan Ayyaswami of Qualcomm, shared four papers with more than 200 users.
- Top Synopsys technologists gave insightful presentations during three vision sessions that drew capacity attendance:
- Brent Gregory, Synopsys Fellow, gave a humorous, futuristic session on "Designing 100 Billion Transistor Chips." Feedback included: "Brilliant, Mr. Gregory! Appreciate the spirit and much-needed perspective on the difficulty of the problem."
- Godwin Maben, Synopsys Scientist and Applications Consultant, presented a well-received presentation on "Low-Power Design: How Long until We Hit the Wall?" Feedback included: "Showed excellent vision in how future power consumption and power savings trends would look like."
- Narendra Shenoy, Synopsys Fellow, spoke about "Semiconductor Trends and Challenges for the Coming Years." Feedback included: "A real vision session—showed the world 10 years ahead."
Don Chan, CAE vice president, chaired an 'Ask the Experts' panel on "Best Practices for High-Performance Processor Core Implementation." Representatives from Xilinx, ARM and Synopsys Global Technical Services answered questions about techniques used in high-performance core implementation.
- The second day of the program concluded with a celebration of the Best Paper Awards winners. Winning user papers included titles such as:
- Gaps and Challenges with Reset Logic Verification
- Techniques to Improve Quality of Memory Interface Tests in SoCs Using Synopsys TetraMAX®'s RAM Sequential ATPG
- HAPS-Based FPGA Prototype of Industrial Communication Subsystem for IP validation and Firmware
- Implementation of ARM Cortex-A9 Quad Core Processor with Synopsys Hierarchical Flow
- Handling Power Challenges for Orphan IPs
- Hybrid Full Chip SPICE Simulation Methodology for Complex Low-Power Mixed-Signal SoC
- Generic MLM environment for SoC Performance Enhancements
SNUG India has been a growing part of the global SNUG program for 13 years. For 22 years, SNUG events worldwide have offered attendees an excellent technical program plus an opportunity to connect with Synopsys executives, design ecosystem partners and the local design engineering community. For more information on future SNUG conferences, visit http://www.synopsys.com/Community/SNUG/Pages/default.aspx.
- Related Links