|From March 25th to 28th, the Santa Clara Convention Center was filled with more than 2500 Synopsys users hungry for information on the latest EDA and IP solutions, semiconductor technology trends and chip design tips and techniques. They were also hungry for a chance to meet in person with their peers and perhaps network during one of the lunch or evening events. SNUG Silicon Valley 2013 served up all that and more. In a survey, attendees rated the technical quality of the conference an impressive 4 out of a possible 5.|
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|Each day kicked off with a visionary keynote. On Monday, Dr. Aart de Geus, Synopsys Chairman and co-CEO presented "Massive Innovation and Collaboration into the 'GigaScale' Age!" Dr. de Geus' comment that the economics of Moore's law are irrelevant raised some eyebrows among the attendees. View Dr. de Geus' keynote to learn why.|
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|Tuesday, Sir Hossein Yassaie PhD, CEO of Imagination Technologies, presented "From Crystal Ball to Reality — The Impact of Silicon IP on SoC Design." Sir Yassaie explained that IP can take up to six years to create, noting that today's SoCs do not reflect tomorrow's. He stressed the importance of paying attention to trends and surprised the audience by encouraging engineers to become more involved in marketing. View Sir Yassaie's keynote to learn why.|
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|Wednesday, Dr. Cliff Hou, vice president of Research & Development at TSMC, presented "Collaborate to Innovate - A Foundry's Perspective on Ecosystem." In this insightful keynote, Dr. Hou described the semiconductor industry as one of the largest business ecosystems in the world where collective diversity and creativity has fundamentally reshaped human society. He also discussed how foundry collaboration with EDA is becoming ever closer, earlier and wider to enable designs concurrently with process development, even especially at the advanced nodes.|
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|In addition to the keynotes, there were 73 technical sessions on wide range of topics including static timing analysis, clock tree synthesis, high-performance core implementation flows and verification with OVM/UVM methodologies. Synopsys users can access SNUG papers through SolvNet.|
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|Designing for FinFET processes was one of the most popular topics this year. The FinFET technical sessions and "Lunch and Learn" were very well attended. The "FinFET Technology and Early Experiences" panel featuring speakers from Samsung, GLOBALFOUNDRIES, Qualcomm and Cavium Networks was standing-room-only.|
Because collaboration between vendors is so critical to silicon success, Synopsys ecosystem partners were given an opportunity to share their solutions at the Designer Community Expo (DCE). This year's DCE offered SNUG attendees access to 63 ecosystem partners as well as to many technical experts from around the industry, all in one place. DCE Silicon Valley was organized into seven designer communities: Compute and Design Infrastructure, Custom Design and AMS Verification, FPGA, IC Design, IC Verification, IP, and System-level, allowing attendees to learn more about the numerous design enablement solutions available. DCE also offers networking opportunities with fellow users, Synopsys technical staff and executives in a relaxed environment with food and drinks around the Expo floor. At SNUG Silicon Valley 2013, DCE hosted more than 950 people throughout the evening. The program will hit the road in 2013 at SNUG events in India, Japan, Boston and Austin.
Additional opportunities for designers to network while enjoying food and drinks included daily luncheons, the PrimeTime SIG dinner and SNUG Pub. Featuring a Grand Prix theme with games, food and drinks, SNUG Pub had the highest attendance ever with over 700 customers participating.
The third day of the program concluded with the Best Paper Award ceremony. Two categories of awards were given. Technical Committee awards recognized the technical excellence of the peer reviewed conference papers. Presentation Awards were selected by a vote of SNUG attendees. Synopsys users can access SNUG papers through SolvNet
- The award winning papers and authors are as follows:
- Technical Committee Awards:
- Best Paper: "No Man's Land - Constraining Async Clock Domain Crossings" by Paul Zimmer of Zimmer Design Services
- Honorable Mention: "Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High-Performance Mobile SoCs" by James Myers, David Flynn and John Biggs of ARM
- Honorable Mention: "Efficient Timing Constraint Analysis and Debug using PrimeTime-GCA" by Peter Lindberg of LSI Corp
- Presentation Awards:
- Best Presentation of Silicon Valley SNUG 2013 Award: "Synthesizing SytemVerilog: Busting the Myth that SystemVerilog is only for Verification" by Don Mills of Microchip and Stuart Sutherland of Sutherland HDL
- Outstanding Conference Presentation Awards: "Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High-Performance Mobile SoCs" by James Myers, David Flynn and John Biggs of ARM;
"Double Patterning Aware Extraction Flows for Digital Design Sign-off in 20/14nm" by Tamer Ragheb of GLOBALFOUNDRIES
Congratulations to all the winners!
For more information about upcoming SNUG events, visit the SNUG website at www.synopsys.com/SNUG.