DAC 2013 

Demo Schedule 

Demo Descriptions

Synopsys provides innovative technology and solutions for implementation and verification. Visit us at Booth #947 to find out more!

Pre-registration is not required, but seating is limited and will be provided on a first-come/first-served basis. We recommend that you arrive 5-10 minutes prior to the demo session you are interested in attending.

Monday, June 3

TimeDemos
10:00-11:00Synopsys Custom Design Solution
10:00-11:00PrimeTime: Latest Advances in Timing Signoff
11:00-12:00Design Compiler: Accelerate Your RTL Exploration and Implementation
1:00-2:00Functional Verification: A Comprehensive Solution for Addressing Rising SoC Challenges
2:00-3:00IC Compiler: Enabling Advanced Designs at All Process Nodes
2:00-3:00PrimeTime: Latest Advances in Timing Signoff
3:00-4:00IC Compiler Custom Co-Design: Seamless Roundtrip Implementation
4:00-5:00Design Compiler: Accelerate Your RTL Exploration and Implementation
5:00-6:00IC Compiler: Enabling Advanced Designs at All Process Nodes

Tuesday, June 4

TimeDemos
10:00-11:00Synopsys Custom Design Solution
10:00-11:00PrimeTime: Latest Advances in Timing Signoff
11:00-12:00IC Compiler: Enabling Advanced Designs at All Process Nodes
1:00-2:00Design Compiler: Accelerate Your RTL Exploration and Implementation
2:00-3:00IC Compiler: Enabling Advanced Designs at All Process Nodes
2:00-3:00PrimeTime: Latest Advances in Timing Signoff
3:00-4:00IC Compiler Custom Co-Design: Seamless Roundtrip Implementation
4:00-5:00Functional Verification: A Comprehensive Solution for Addressing Rising SoC Challenges

Wednesday, June 5

TimeDemos
10:00-11:00IC Compiler: Enabling Advanced Designs at All Process Nodes
10:00-11:00PrimeTime: Latest Advances in Timing Signoff
11:00-12:00Design Compiler: Accelerate Your RTL Exploration and Implementation
2:00-3:00PrimeTime: Latest Advances in Timing Signoff

Demo Descriptions


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