DAC 2012 


Synopsys provides innovative technology and solutions for implementation, verification and system-level design. Visit us at Booth #1130 to find out more!

Seating is limited and will be provided on a first come, first serve basis. We recommend that you arrive 5-10 minutes prior to the demo session you are interested in attending.

  • IC Compiler and IC Validator: The Best Solution for DPT-Compliant 20nm Designs
    Learn how IC Compiler and IC Validator In-Design technology address 20nm design challenges. IC Compiler Zroute 20nm readiness and DPT aware placement and routing are showcased to demonstrate how you can achieve high-quality implementation and manufacturability for predictable design closure.
  • IC Compiler Custom Co-Design
    Learn how the IC Compiler Custom Co-Design solution enables design teams to easily move between digital and custom implementation flows, while maintaining design data integrity. The unified solution accelerates the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development, including the time-critical tapeout phase. See how Galaxy Custom Designer®, with tight integration to IC Compiler, enables higher productivity through advanced features such as DRC/LVS-correct interactive mixed-signal auto-routing and DRC-aware custom editing.
  • Next-Generation Discovery™ Verification IP, including Protocol Analyzer
    Discovery VIP is a new generation of VIP written 100% in SystemVerilog with native support for UVM, OVM and VMM. This tutorial will explain the underlying VIPER architecture that enables superior performance and ease-of-use compared to today's first generation VIPs. It will show new productivity features built on the VIPER architecture for rapid deployment, high performance, easier debug and quick coverage closure. The tutorial will conclude with a demonstration of a unique, protocol-aware debug environment, and show how it can be used to quickly find the root-cause of a problem on a ARM® AMBA®4 ACE™ design.
  • Integrating Virtual Prototypes in the Development of SoCs
    As the software content of system-on-chips and end products grows, semiconductor development teams are integrating new technologies to develop and debug software as early as possible in their development cycle. This session will highlight how virtual prototypes enable hardware and software engineers to start software development 12 months or more before silicon, and accelerate the hardware verification and system validation tasks.

Demo schedule

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