Synopsys at DAC 2013
Accelerating Innovation—that has been at the heart of Synopsys’ commitment to its customers for more than 25 years. As a leader in EDA and semiconductor IP, Synopsys’ software, IP and services help engineers address their design, verification, system and manufacturing challenges and accelerate their innovations.
How can Synopsys help you accelerate your innovation? See us at the Design Automation Conference (DAC) June 2 - 6 in Austin, Texas, booth #947.
Event List: Description and location of all DAC events
Partners and Standards
A New Text Book on Timing Constraints
Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)
Sridhar Gangadharan (Atrenta) and Sanjay Churiwala (Xilinx)
The book targets system on chip designers and provides a complete overview of how to create effective timing constraints using SDC, including detailed syntax and semantics, its impact on timing analysis and synthesis and the interaction of timing constraints with the rest of the design flow.
"Timing has become a critical requirement for the highly complex system on chip designs we see today and effective use of SDC is critical to success," said co-author Sridhar Gangadharan, senior product director at Atrenta. "I would like to acknowledge Synopsys for their work to develop the Synopsys Design Constraints (SDC) format and their willingness to make it widely available through their TAP-in program."
The following new and updated courses are now available. Visit Members Only with your SolvNet ID and password to download.
- Call for Papers