Researchers at SMU are in the forefront of research concerning Multiple-Valued Logic circuit design and EDA algorithms. Papers [1,2,3] cite the use of Synopsys VCS and SystemVerilog constructs that support the modeling and analysis of MVL circuits. The work in [4] cites the use of DesignCompiler, HSPICE, VCS, and PrimeTime for work in arithmetic circuit design for new architectures involving fixed-point squaring circuits. A new UML based synthesis approach for embedded system design is reported in [5] that uses SystemVerilog and associated Synopsys tools.

[1] Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits
S. Datla and M.A. Thornton, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 26-28, 2010, pp. 128-133.

[2] Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog
S. Datla, M.A. Thornton, L. Hendrix, and D. Henderson, IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 21-23, 2009, pp. 256-261.

[3] Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
M. Amoui, D. Grosse, M.A. Thornton, and R. Drechsler, IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2007, electronic proceedings, Session 8B, paper 2.

[4] A Low Power High Performance Radix-4 Approximate Squaring Circuit
S. Datla, M.A. Thornton, and D.W. Matula, IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), July 7-9, 2009, pp. 91-97.

[5] UML to SystemVerilog Synthesis for Embedded System Models with Support for Assertion Generation
L. Li, F.P. Coyle, and M.A. Thornton, Proceedings of the ECSI Forum on Design Languages, September 18-20, 2007, Paper 10 on CD-ROM.