TLMCentral, an industry-wide web portal that offers a unique aggregation point for transaction-level models, is adding an open source component to its model portal capabilities. With this new feature, model developers can upload their open source SystemC TLM-2.0 based models, adding to the 800+ list of commercially available models now on the site. To kick off this new addition to the portal, TLMCentral is hosting a model contest with opportunities to win an iPad 2. Go to www.tlmcentral.com to learn more.
The Synopsys 90nm Generic Library has recently been updated and is currently available for download. The latest updated version contains all bug fixes done since the last release (January 27, 2011) as a result of the ongoing maintenance process of EDK. The Synopsys 90nm Generic Library enables students to master advanced design methods, such as low power, using the latest Synopsys EDA tools. It includes: digital and I/O standard cell libraries, memories, a phase-locked loop, a technology kit and a couple of sample designs. The library is also compatible with the OpenSPARC T1 and IBM PowerPC 405 architectures. For more information about the library please see the 90nm Generic Library FAQ.
The following new and updated courses are now available. Visit Members Only with your SolvNet ID and password to download.
Low Power Methodology Manual - New!
VLSI Physical Design Algorithms - Updated!
Programming Languages and Compilers - Updated!
Reliability Analysis of Power Gated SRAM under Combined Effects of NBTI and PBTI in Nano-Scale CMOS
Anuj Pushkama & Hamid Mahmoodi
Full-Custom Design Project for Digital VLSI and IC Design Courses using Synopsys Generic 90nm CMOS Library
Adaptive Supply Voltage Circuit Using Body Bias Technique
Mina Raymond, Maged Ghoneima & Yahea Ismail
New Subthreshold Concepts in 65nm CMOS Technology
ISDRS 2011 (International Semiconductor Device Research Symposium)
December 7-9, 2011
College Park, Maryland
ISFPGA (International Symposium on Field-Programmable Gate Arrays)
February 26*28, 2011
IWIA 2012 (International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems)
January 9-11, 2012
Kohala Coast, Hawaii
IEDEC 2012 (Interdisciplinary Engineering Education Conference)
March 19-20, 2012
Santa Clara, California
Call for Papers
Due By: January 15, 2012