Synopsys has developed a 90nm Interoperable PDK for its University Program members to use in teaching microelectronic design. This new PDK enables students to master design of analog and mixed-signal integrated circuits and IP using the latest Synopsys Custom Implementation tools.
|90nm PDK Basics |
- Based on the OpenAccess Database
- Optimized for use with Synopsys' Custom Implementation tools
- Requires Synopsys University EULA and click-thru addendum
- Not designed for fabrication
90nm PDK Content
Technology files include the Custom Designer technology file, display resource files and layer map file.
Physical Verification Files
Physical verification files include Hercules DRC and LVS decks.
Parasitic Extraction Files
StarRC parasitic extraction files include ITF file, mapping file and nxtgrd file.
Symbol Library and OA Python PCells
Symbol library contains 24 variants of device symbols for MOS, resistor, capacitor, diode, BJT, inductor and varactor. Symbols have up to 50 customizable parameters. Symbols also contain PCells.
HSPICE models include simulation models for different devices including: MOS, resistor, capacitor, diode, etc.
Callback scripts include invalid input checks, integer checks for parameters (m, nf, series, parallel etc), min/max and off-grid checks for non-variable inputs and display warning/error messages.
Documentation and Set-up Files
Documentation includes a design rules document and databook that describes the technical and symbol library parameters and PCells. Setup files are used to set-up the PDK for use with Custom Designer.
The 90nm Interoperable PDK includes reference designs for invertor and nand.
The 90nm Interoperable PDK is now available in Members Only for Synopsys University Program members to download. You must have your SolvNet ID and password to access.