32/28nm Interoperable PDK 

Synopsys 32/28nm Interoperable PDK for Teaching AMS/Custom Design   

Synopsys has developed a 32/28nm Interoperable PDK for its University Program members to use specifics of modern technologies in teaching microelectronic design. This new PDK enables students to master design of analog and mixed-signal integrated circuits and IP using the latest Synopsys Custom Implementation tools and utilizing IP free technology with parameters and peculiarities close to real processes.

32/28nm PDK Basics
  • Set of all necessary data for starting AMS/Custom design
  • Based on the OpenAccess Database
  • Optimized for use with Synopsys' Custom Implementation tools
  • Requires Synopsys University EULA and click-thru addendum
  • Not designed for fabrication

32/28nm PDK Content

32/28nm PDK Content

Technology Files
Technology files include technology, display resource files and layer map files. These contain layer information, design rule definitions, etc.

Physical Verification Files
Physical verification files include Hercules and IC Validator DRC and LVS runset files. DRC runsets include a density check, a dummy layer fill and antenna check runsets.

Parasitic Extraction Files
StarRC parasitic extraction files include ITF file, mapping file and nxtgrd file.

HSPICE models include simulation models for different devices including: MOS, resistor, capacitor, diode, etc.

Symbol Library and OA Python PCells
Symbol library contains 24 variants of device symbols for MOS, resistor, capacitor, diode, BJT, inductor and varactor. Symbols have up to 50 customizable parameters. Symbols also contain PCells.

Callback Scripts
Callback scripts include invalid input checks, integer checks for parameters (m, nf, series, parallel etc), min/max and off-grid checks for non-variable inputs and display warning/error messages.

Documentation includes a design rules document, databook that describes the technical and symbol library parameters and PCells, model usage guide and device formation reference.

The 32/28nm Interoperable PDK includes reference designs for invertor, NAND and flip-flop

Design Environment Setup Files
The 32/28nm Interoperable PDK Process Design Kit contains scripts for environment setup which assure correct operation of all the components.

The 32/28nm Interoperable PDK is now available in Members Only for Synopsys University Program members to download. You must have a valid SolvNet ID and password to access. To request support for the 32/28nm Interoperable PDK, contact us.

"The Synopsys Generic 90nm and 32/28nm iPDK and Library are excellent resources for research. These resources have enabled us to establish comprehensive ASIC design and verification flows that are used in our teaching and research activities."
— Hamid Mahmoodi, Assistant Professor of School of Engineering, San Francisco State University

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