| Time | Description |
| 8:30-9:30 | Registration and Breakfast |
| 9:30-10:15 | Welcome & Introduction: Mike Bartley, UK SNUG Technical Chair, TVS Ltd.
Video Message: Aart De Geus, CEO Synopsys, Inc,
Program Overview and Logistics: Peter Bell, Senior Technical Manager, Synopsys UK |
| 10:15-10:45 | Break |
| 10:45-12:15 | A1 Tutorial Session
FPGA Implementation and FPGA-based Prototyping I | A2 User & Tutorial Session
Low Power | A3 Tutorial & User Session
Front End Implementation & Signoff I | A4 Tutorial & User Session
Verification I | A5 Tutorial & User Session
AMS / Full Custom Design I | A6 User & Tutorial Session
Design for Test
|
| 12:15-13:30 | Lunch |
| 13:30-15:00 | B1 User & Tutorial Session
FPGA Implementation and FPGA-based Prototyping II | B2 Tutorials
Back End Implementation I | B3 Tutorial & User Session
Front End Implementation & Signoff II | B4 User Session
Verification II | B5 User and Tutorial
AMS / Full Custom Design II | B6 Tutorial & User Session
Lynx Design System |
| 15:00-15:30 | Break |
| 15:30-17:00 | C1 User & Tutorial Session
FPGA Implementation and FPGA-based Prototyping III | C2 User & Tutorial Session
Back End Implementation II | C3 User & Tutorial Session
Front End Implementation & Signoff III | C4 User & Tutorial Session
Verification III | C5 Tutorial Session
AMS / Full Custom Design III | C6 Tutorial Session
Design IP |
| 17:00-18:00 | |