SNUG search results 


28nm FD-SOI FlipChip Design with IC Compiler II - France, 2016
Raphael Theveniau - STMicroelectronics; Alain Boyer - Synopsys
PaperPresentation

3D Stacked Sensor Prototyping using HAPS-70: Maximizing HAPS Utilization by using a Multi Design Approach - France, 2016
Hubert Deborgies - STMicroelectronics
PaperPresentation

A GVI SystemVerilog Nettype Ready for Mixed-signal Simulations - France, 2016
Sebastien Cliquennois, Francois Ravatin - STMicroelectronics
PaperPresentation

A New Methodology for Automotive Design Robustness to Defects, Using Certitude at RTL and Gate Netlist Level - France, 2016
Hubert Marcel, Aymeric Leroy - STMicroelectronics
PaperPresentation

Accelerate Your FPGA Design Schedules with Synplify Premier - France, 2016
Tutorial

Adapt, Port, and Integrate Quickly - Prototyping the Right Way - France, 2016
Tutorial

Alternative DFT Solutions to Cope with Physical Congestion - France, 2016
Matthieu Sautier, Mohamedarif Alarakhia, Rachid Idrissi - STMicroelectronics
PaperPresentation

AMS MASIS Wrapper Usage for Efficient Test Control - France, 2016
Livier Lizarraga, Cédric Escallier - STMicroelectronics
Publish Only

AMS Simulation Update - France, 2016
Tutorial

Conclusive Formal Verification of Clock Domain Crossings using SpyGlass-CDC - France, 2016
Mejid Kebaili, Jean-Christophe Brignone - STMicroelectronics; Guillaume Plassan, Jean-Philippe Binois - Synopsys
PaperPresentation

Custom Compiler - Assisted Layout Automation Walk-Through Demo - France, 2016
Tutorial

Debug an ADC Design with UPF Support in Verdi - France, 2016
Tutorial

Designing Safer Cars - A Journey in ISO 26262 Territories - France, 2016
Tutorial

DFTMAX-Ultra to Enable High Test Coverage for an Ultra-Low Pin Count Design Embedding a Test Mode Controller - France, 2016
Mohrad Mammasse - STMicroelectronics
PaperPresentation

Fast Yield Ramp by Correlating Failed Test Diagnostics and Fab-related Design Hotspots - France, 2016
Nelly Feldman - STMicroelectronics; Christophe Suzor, Salvatore Talluto - Synopsys
PaperPresentation

Floorplanning Large Blocks Using IC Compiler II - France, 2016
Tutorial

Formality Complete Low Power Verification and Formality 2016.03 Update - France, 2016
Tutorial

FPGA Prototyping of a Complete System-on-Chip with the HAPS-DX7 - France, 2016
Sandro-Diego Wölfle - Hyperstone GmbH
PaperPresentation

How Flexible Debug Can Speed Physical Prototype Bring-Up and Software Development - France, 2016
Tutorial

Improve Predictability and Routability by Anticipating CTS Routing Topology - France, 2016
Luc Sponga, Corine Pulvermuller - STMicroelectronics; Sébastien Paquet - Synopsys
PaperPresentation

Improved Turnaround Time and Performance using Parametric OCV in 28nm FD-SOI Technology - France, 2016
Tarun Chawla - STMicroelectronics
PaperPresentation

In-design Track Fill in IC Compiler II - France, 2016
Didier Gueze - STMicroelectronics
PaperPresentation

Innovative Propagation Methodology for Diodes and Clamps by Using TCL-CCK Advanced Capabilities in Synopsys Circuit Check - France, 2016
Luca Togni, Mauro Fragnoli, Paolo Ghigini, Salvatore Santapa, Pierluigi Daglio, Alessandro Valerio - STMicroelectronics; Carlo Borromeo - Synopsys
PaperPresentation

Insights about Ageing Simulation with Fast SPICE CustomSim (XA) Memory Applications at STMicroelectronics - France, 2016
Florian Cacho, Atul Bhargava, Radhika Gupta, Dorfy Rao - STMicroelectronics
PaperPresentation