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FA1.1 - Sequential Logic Duplication for Front-End Design - Austin, 2014
Christopher Stites - Advanced Micro Devices
PaperPresentation

FA1.2 - Front-End Method for IO Port Constraint Optimization and Convergence - Austin, 2014
Brian Walters, Christopher Stites - Advanced Micro Devices
PaperPresentation

FA1.3 - UPF Refinement – Considerations and Application - Austin, 2014
Tutorial

FA2.2 - Top Level Design Closure Made Easy - Austin, 2014
Bijoy James - Altera Corporation
PaperPresentation

FA2.3 - PrimeTime ECO - Now Physically Aware - Austin, 2014
Tutorial

- Austin, 2014
Synopsys, Inc.

FA4.1 - Getting Results with Xilinx's Stacked Silicon Interconnect Devices - Austin, 2014
Rich Wiegard - Xilinx, Inc.
Presentation

FA4.2 - Integrating Siloti into Live FPGA Debug - Austin, 2014
Tutorial

FA4.3 - Test IP - Bringing the Tools and Methodology from Pre-Silicon Verification to Post-Silicon Validation - Austin, 2014
Al Czamara, Richard Proto, Paul Tomashevskyi - Test Evolution
PaperPresentation

FA5.1 - Embedded SRAM Analysis and Characterization Using NanoTime for Memories - Austin, 2014
Robert Murray - NVIDIA; Felipe R. Schneider - Synopsys, Inc.
PaperPresentation

FA5.2 - A Complete Static Crosstalk Noise Analysis Flow Using NanoTime - Austin, 2014
Stephen Lim, David Newmark - Advanced Micro Devices; Frank Yang, Maureen Ladd - Synopsys, Inc.
PaperPresentation

FA5.3 - Parametric On-Chip Variation (POCV) Characterization with SiliconSmart - Austin, 2014
Lyren Brown, David Newmark - Advanced Micro Devices; Myles Prather - Synopsys, Inc.
PaperPresentation

FB1.1 - Using the New Placement-Aware Multibit Register Mapping in Design Compiler Graphical - Austin, 2014
Ken Umino, Hyon Han - Samsung Advanced Research Center; LaMark Chance, Sharrone Smith - Synopsys, Inc.
PaperPresentation

FB1.2 - Functional ECOs Made Easier with Formality Ultra - Austin, 2014
Tutorial

FB2.1 - Leveraging the Lynx Design System - Austin, 2014
Steve Cline - Altera Corporation
Presentation

FB3.1 - Handling Windows of Uncertainty - Reducing False Errors from Variable DUT Timing - Austin, 2014
Jeffery Vance - Verilab
PaperPresentation

FB3.2 - Reality and Challenges in Using Save/Restore in SoC Verification Environment - Austin, 2014
Satish Naidu, Amol Bhinge - Freescale Semiconductor
PaperPresentation

FB4.1 - From Formal Apps to End-to-End Verification - Formal Analysis for Everyone! - Austin, 2014
Tutorial

FB4.2 - How Do You Know When Your Test Is Broken? Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions - Austin, 2014
Kelly D. Larson - Paradigm Works
PaperPresentation

FB5.1 - ATPG Techniques and Methodology for Low-Power High Effectiveness Pattern Generation in a High Performance Quad-Core CPU Design - Austin, 2014
Kelvin Ge, Vivek Ramnath - Samsung Electronics
PaperPresentation