SNUG search results 


A Comprehensive UVM Verification Environment for MPEG Transport-Stream Processing - France, 2015
Filippo Borlenghi, Simone Borri, Gherardo Gorni - ALi Europe
PaperPresentation

A53 Core Optimization to Achieve Performances - France, 2015
Calogero Timineri, Julien Buvat, Julien Guillemain, Sébastien Peurichard - STMicroelectronics
PaperPresentation

Achieving Optimal Quality of Results Faster with Design Compiler - France, 2015
Tutorial

Adopting UVM Methodology for IP Level Verification - France, 2015
Giovanni Auditore, Francesco Rua' - STMicroelectronics
PaperPresentation

Advanced Synthesis Technique Using Target Library Subset - France, 2015
Laurent Besson - STMicroelectronics
PaperPresentation

Automated Flow for High DC Current Verification - France, 2015
David Turgis, Faress Tissafi Drissi - STMicroelectronics
PaperPresentation

Automatic Feed-through Parasitic Extraction for Memory Compiler Spice Simulations - France, 2015
Fabien Leroy - ARM
PaperPresentation

Best Practices for Implementing ASIC designs to FPGAs and Boosting Timing Performance (Tips and Techniques from the Field) - France, 2015
Tutorial

CCS Noise Library Generation and Checking - France, 2015
Benoît Lasbouygues - Atmel Corporation
PaperPresentation

EM/IR Verification of a 14FDSOI Video DAC Using CustomSim-RA - France, 2015
Alejandro Chimeno, Francois Lemery, Véronique Bessodes, Nicolas Pelloux - STMicroelectronics
PaperPresentation

Extending New Verification Techniques to Mixed-Signal SoCs with VCS AMS - France, 2015
Pierluigi Daglio, Mauro Scandiuzzo, Alessandro Valerio - STMicroelectronics; Helene Thibieroz, Massimo Prando, Carlo Borromeo - Synopsys
PaperPresentation

Fast ECO Extraction and Other Techniques for Optimizing Timing Closure TAT - France, 2015
Tutorial

FDSOI - An Interoperable Technology - France, 2015
Gilles Namur - STMicroelectronics
Presentation

Formal Qualification of Functional and Connectivity Formal Verification Environments at SoC Level Using Synopsys Certitude - France, 2015
Massimo Zendri - STMicroelectronics
PaperPresentation

Handling Electromigration for Custom Design with FinFET Devices Using Custom Designer - France, 2015
Tutorial

Harnessing the Power of AMS-testbench for Verifying a Mixed-signal SoC environment - France, 2015
Tutorial

High-end Test Compression Methodology for Low Pin Count Products in Secured Environment - France, 2015
Caroline Carin, Arnaud Donné - STMicroelectronics
PaperPresentation

How to Achieve a Working FPGA Prototype Faster by Using a Transactor-based Prototyping Flow - France, 2015
Tutorial

ICC/ICC II Physical Implementation Comparison of a GPU Partition - France, 2015
Anna Asquini, Corine Pulvermuller - STMicroelectronics; Vincent Sornette - Synopsys
PaperPresentation

In-Design Metal Fill Insertion for Faster Timing Convergence - France, 2015
Raphael Gras, Ahmed Oumina - STMicroelectronics; Emmanuel Pluchart - Synopsys
PaperPresentation

Latest Advancements for Handling Local Variation Effects in Timing Analysis - France, 2015
Tutorial

MAXtestbench - A Technology to Manage STIL Pattern Qualification in Complex SoC Verification Environment - France, 2015
Guillaume Costrel de Corainville, Mickael Broutin - STMicroelectronics
PaperPresentation

Meet Your Test Quality and Cost Goals on Schedule - France, 2015
Tutorial