SNUG Awards 

1st Place - Best Paper
Austin
DFT Architecture and Implementation of a Quad-core ARM® Cortex™ Processor Targeted for Low-Power, High Performance Applications
Author(s): Kelvin Ge, Shaishav Parikh - Samsung, Glenn Boyer - Synopsys
PaperPresentation


BostonSuccessful Multi-Voltage Design: Using Power-aware Equivalence Checking and Static MV Analysis to Boost Tape-out Confidence
Author(s): Conor Byrne, Padraig Golden, Venkatesh Jakke - Intel
PaperPresentation


CanadaThe Clear Advantages of Multi-Source CTS
Author(s): Sid Allman - Cisco Systems
PaperPresentation


FranceConcurrent Top and Blocks Level Implementation of a High-Performance Graphics Core using One-Pass Timing Closure in Synopsys ICC
Author(s): Corine Pulvermuller, Julien Guillemain - STMicroelectronics
PaperPresentation


GermanyApplying Synopsys Physical Guidance (SPG) Methodology to Address Complex 28nm Design Challenges
Author(s): Jürgen Dirks - LSI
PaperPresentation


Silicon ValleyMC3-B Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification
Author(s): Don Mills - Microchip Technology; Stuart Sutherland - Sutherland HDL, Inc.
PaperPresentation


UKComplex SOC Prototyping using Xilinx Virtex 7 based HAPS-70 Systems
Author(s): Paul Robertson - Broadcom, Andy Jolley - Synopsys Ltd.
PaperPresentation

2nd Place - Best Paper
Austin
Using PrimeTime's New Signoff-Driven Leakage Recovery Feature
Author(s): Hyon Han, Shen Ge, Dean Marvin, Ashish Nayak , Francis Skowronski - Samsung
PaperPresentation


BostonCoverage Closure and Debug Using Symbolic Simulation
Author(s): Courtney Schmitt - Analog Devices, Inc.; Manoharan Vellingiri, Alex Wakefield - Synopsys
PaperPresentation


Corner Wiring and Via Placement Made Easy in Custom Designer Layout Editor
Author(s): James Cherry - Kapik Inc.
PaperPresentation


CanadaFPGA Continous Integration with Jenkins
Author(s): Martin d’Anjou - Ciena
PaperPresentation


France28nm FDSOI Leakage Optimisation with Synopsys Flow
Author(s): Pascal Teissier - STMicroelectronics, Nathalie Zaghlan - Synopsys
PaperPresentation


GermanyStatic Noise Analysis Including Power Noise
Author(s): Sönke Grimpen - Infineon
PaperPresentation


Silicon ValleyDouble Patterning Aware Extraction Flows For Digital Design Sign-Off in 20/14nm
Author(s): Adrian Au Yeung, Steven Chan, Hendrik Mau, Rick Monga, Tamer Ragheb, Venkat Ramasubramanian, Richard Trihy - GLOBALFOUNDRIES
PaperPresentation


UKArchitecting Power Awareness in a Constrained Random OVM Testbench
Author(s):
PaperPresentation

3rd Place - Best Paper
Austin
Accurate Transistor-level STA Methodology for 20nm Custom SRAM Macro Using NanoTime
Author(s): Shahnaz Nagle, Mandeep Singh - Samsung, Charles Jiang - Synopsys
PaperPresentation


CanadaUVM-Based Vertical DV Re-use in Packet Processing ASICs
Author(s): Karim Khordoc, Dennis Im, Lawrence Said - Cisco Systems
PaperPresentation


FranceConverting an Outdated Library for UPF Compliancy Prior to a Low-Power Physical Design that uses Retention Flip-Flops
Author(s): Etienne Wouters, Ilse Vos - IMEC
PaperPresentation


GermanyNext-Generation Prototyping - a Hybrid Approach
Author(s): Peter Blöcher, Uwe Grüner - ST-Ericsson
PaperPresentation


Silicon ValleyMA06-A "No Man's Land" - Constraining Async Clock Domain Crossings
Author(s): Paul Zimmer - Zimmer Design Services
PaperPresentation


UKCertitude - Achieving Faster Verification Closure Using Design Mutation Analysis
Author(s): Yogish Sekhar - Dialog Semiconductors
PaperPresentation

Best Paper Award
Israel
Implementing UPF Flow for SoC Design
Author(s):
PaperPresentation


TaiwanA Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests
Author(s): Richard Tseng, Qualcomm
PaperPresentation


Does Power State Table Matter in Low Power Verification?
Author(s): Shang-Wei Tu, MediaTek
PaperPresentation


Achieving Timing Closure on Hundred Million Gates SoC Design with ETM & ILM
Author(s): Chi-Chia Yu - Faraday
PaperPresentation

Technical Committee Award
Boston
Successful Multi-Voltage Design: Using Power-aware Equivalence Checking and Static MV Analysis to Boost Tape-out Confidence
Author(s): Conor Byrne, Padraig Golden, Venkatesh Jakke - Intel
PaperPresentation


CanadaThe Clear Advantages of Multi-Source CTS
Author(s): Sid Allman - Cisco Systems
PaperPresentation


FranceAdvanced CTS Techniques for High-Performance Mobile Designs
Author(s): Frank Vaneerdewegh - ST-Ericsson
PaperPresentation


GermanyCertitude and VCS at Module-level: a User's Experience
Author(s): Stephanie Legeleux, Andreas Pachl, Rafael Pena Bello - Freescale Semiconductor
PaperPresentation


IsraelFeed Through Insertion at Hierarchical Design Flow
Author(s): Gilad Konsker, Avi Zukerman - CSR
PaperPresentation


Silicon ValleyMA06-A "No Man's Land" - Constraining Async Clock Domain Crossings
Author(s): Paul Zimmer - Zimmer Design Services
PaperPresentation


UKPower Intent Specification: Successful Integration of Hard Macros
Author(s):
PaperPresentation


Technical Committee Award Honorable Mention
France
Advanced Technologies FRAM View Generation Methodology
Author(s): Sylvain Landelle, Sophie Rabadan - STMicroelectronics, Eric Bouet - Synopsys
PaperPresentation


GermanyHigh-Level Power Modeling with Synopsys Platform Architect - A Signal Processing Use-Case
Author(s): Bernhard Fischer, Christian Cech - Siemens
PaperPresentation


Silicon ValleyMA06-B Efficient Timing Constraint Analysis and Debug using PrimeTime-GCA
Author(s): Peter Lindberg - LSI Corp.
PaperPresentation


TC1-A Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High Performance Mobile SoCs - Technical Committee Award, Honorable Mention
Author(s): John Biggs, David Flynn, James Myers - ARM
PaperPresentation


UKMaking the Most of SystemVerilog and UVM: Hints and Tips for New Users
Author(s): David Long - Doulos
PaperPresentation