SNUG Awards 

1st Place - Best Paper
Austin
Taming Testbench Timing: Time's Up for Clocking Block Confusion
Author(s): Jonathan Bromley, Kevin Johnston (Verilab)
PaperPresentation


BostonClocks Against Variation
Author(s): Gerard M. Blair (LSI Corporation)
PaperPresentation


CanadaIntegrating SVN Revision Control Software with Synopsys Custom Designer
Author(s): James Cherry (Kapik Integration)
PaperPresentation


FranceEfficient Flow for the Debug of Compressed Scan Patterns During Serial Simulations
Author(s): Sébastien Rousset, Mathieu Thomas [Scaleo Chip]
PaperPresentation


GermanyEfficient Common Derating for Synopsys Implementation Tools
Author(s): Sönke Grimpen - Infineon Technologies AG
PaperPresentation


Silicon ValleyOptimizing Test Times using a Scan Deserializer/Serializer Architecture
Author(s): Milind Sonawane, Jonathon E Colburn, Amit Sanghani [NVIDIA Corp.]
PaperPresentation


SingaporeManaging Test Power Consumption on complex SoC
Author(s): Shibu Menon, Santhosh Sagar Potharam (ST-Ericcson)
PaperPresentation


Circuit Check enhancements to reduce false violations for Low Power Design
Author(s): Samaksh Sinha, Ma Fan Yung, Arumugam Saravanan, Luong Nguyen (Infineon Technologies Singapore)
PaperPresentation


UKProperty Checking of Datapath using Word-Level Formal Equivalency Tools
Author(s): Theo Drane [Imagination Technologies], Himanshu Jain [Synopsys, Inc]
PaperPresentation

2nd Place - Best Paper
Austin
High Performance Physical Design of a 28nm Quad-Core ARM Cortex-A15 with 4 MB L2 Cache
Author(s): Jason Karka, Michael Robinson (Texas Instruments); Bill Sicaras (Synopsys, Inc.)
PaperPresentation


BostonTargeting IBM’s 45nm SOI Process with IC Compiler
Author(s): Nimit Nguansiri (The MITRE Corporation)
PaperPresentation


CanadaA Perspective on Soft and Default Constraints
Author(s): Karim Khordoc (Cisco Systems); Jason Chen (Synopsys, Inc.);
Paper


FranceReal Voltage Modeling through Assertions
Author(s): Ankita Arya, Mohit Jain, Chandan Singh [STMicroelectronics]
PaperPresentation


GermanyClock Gating Analysis in Primetime-PX to Optimize Clock Gating Efficiency
Author(s): Juergen Karmann, Joachim Voges - Infineon Technologies AG
PaperPresentation


Silicon ValleyX-Propagation: An Alternative to Gate Level Simulation
Author(s): Adrian Evans, Julius Yam, Craig Forward
PaperPresentation


SingaporeDesign Compiler Graphical in FPGA Designs
Author(s): Gan Chong Gim (Altera)
PaperPresentation


Improving System Gate-Level Simulation Using VCS New Features
Author(s): Lawrence M. Salazar (BiTMICRO Networks, International Inc.)
PaperPresentation


UKDFT for Fragmented Digital Blocks in Mixed Signal Designs
Author(s): Richard Illman [Dialog Semiconductor]
PaperPresentation

3rd Place - Best Paper
Austin
Qualcomm DSP Semi-Custom Design Flow: Leveraging Place and Route Tools in Custom Circuit Design
Author(s): Nadeem Eleyan, Patrick Szabo, Ken Lin, Paul Bassett, Masud Kamal (Qualcomm), Frank Glover (Synopsys, Inc.)
PaperPresentation


BostonAssert Your Independence! Adopting the OVL Assertion Library as an IP/SoC Standard
Author(s): John A. Thomson (Advanced Micro Devices)
PaperPresentation


CanadaInsight Into Power Gating Verification
Author(s): Ashwini Chandrashekhara Holla (Advanced Micro Devices)
PaperPresentation


FranceUsing TetraMax Top Level Protocol Generation to Extract DFTMAX Codec Information for Lifetest Pattern Generation (HTOL)
Author(s): Gerald Briat, Stéphane Guilhot [ST-Ericsson], Philippe Rossant [Synopsys]
PaperPresentation


GermanyBest Practices of Hierarchical Design Implementation Strategies
Author(s): Norbert Mueller - LSI
PaperPresentation


Silicon ValleyDeveloping and Implementing a Flip Chip Interface using IC Compiler
Author(s): Prasanth Koduri, Sampath Oks, Anupam Gangopadhyay, Santhosh Pillai [Samsung], Susheel Sharma [Synopsys, Inc.]
PaperPresentation


SingaporeLeakage Power Optimization Techniques in High-Speed Design
Author(s): Chin Hsiao Chia, Chen Yung Ching (Mediatek Singapore)
PaperPresentation


Enable Advanced Custom Designer Usage Model with P-Cells Creator and SDL Translation
Author(s): Nam Nguyen, Hieu Vu, Trung Nguyen, Minh Dinh, Nhan Phan (eSilicon Vietnam)
PaperPresentation


UKMaking the most of FPGA Prototyping with the Universal Multi-Resource Bus (UMRBus)
Author(s): Paul Robertson [Broadcom]
PaperPresentation

Best First-Time Presenter
Silicon Valley
Optimizing Test Times using a Scan Deserializer/Serializer Architecture
Author(s): Milind Sonawane, Jonathon E Colburn, Amit Sanghani [NVIDIA Corp.]
PaperPresentation

Best Paper Award
France
Efficient Flow for the Debug of Compressed Scan Patterns During Serial Simulations
Author(s): Sébastien Rousset, Mathieu Thomas [Scaleo Chip]
PaperPresentation


GermanyEfficient Common Derating for Synopsys Implementation Tools
Author(s): Sönke Grimpen - Infineon Technologies AG
PaperPresentation


UKProperty Checking of Datapath using Word-Level Formal Equivalency Tools
Author(s): Theo Drane [Imagination Technologies], Himanshu Jain [Synopsys, Inc]
PaperPresentation

Technical Committee Award
Austin
Advanced Design Partitioning with IC Compiler Leveraging Physical Synthesis
Author(s): Jack Randall (Advanced Micro Devices, Inc.)
PaperPresentation


CanadaI Upped My Coverage, Up Yours!
Author(s): Martin Salomon (STMicroelectronics, Inc.)
Paper


FranceAdvanced Design Flow for LPDDR2 non Volatile Memory Design
Author(s): Anna Faldarini, Christophe Laurent [Micron Technology]
PaperPresentation


GermanyDC Explorer - Fast Synthesis for Early Design Exploration
Author(s): Herbert Taucher, Andras Rappai - Siemens AG ; Rolf Ferner - Synopsys
PaperPresentation


Silicon ValleyAn ARM Cortex-M0 for Energy Harvesting Systems: A Novel Application of UPF with Synopsys’ Galaxy Platform
Author(s): Jatin Mistry [University of Southampton], James Myers [ARM Ltd.]
PaperPresentation


UKI Spy with My VPI: Monitoring Signals by Name, for the UVM Register Package and More
Author(s): Jonathan Bromley [Verilab]
PaperPresentation


Technical Committee Award Honorable Mention
France
Design Optimization and Formal Checking with Retiming Techniques
Author(s): Philippe Maneta [ST-Ericsson]
PaperPresentation


Silicon ValleyUniversal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure
Author(s): Ravi Ram, Warren Anderson, Shyam Sivakumar [Advanced Micro Devices, Inc.], Vijay Akkaraju [Synopsys, Inc.]
PaperPresentation


X-Propagation: An Alternative to Gate Level Simulation
Author(s): Adrian Evans, Julius Yam, Craig Forward
PaperPresentation


UKTiming Sign-off with Statistical Variability: Advanced On-Chip-Variation Modelling (AOCVM) - the theory and the practice
Author(s): Andrew Appleby, Touqeer Azam, Sonia Caldwell, Feng Hong, Mark Scoones [CSR]
PaperPresentation