SNUG Awards 

1st Place - Best Paper
Boston		Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Author(s): Clifford Cummings [Sunburst Design, Inc.]
PaperPresentation

EuropeAutomating Saber with TCL/TK and AIM: Electrical Load Extrapolation and Schematic Generation
Author(s): Jörg Christoffers [EADS Innovation Works]
PaperPresentation

India
Sign-Off
Taping Out Very Large 65nm ASIC Designs in Affordable TAT using StarRCXT, PrimeTime, Hercules
Author(s): K. A. Rajagopal, Thenappan Meyyappan, Ramesh Guzar, Suravi Bhowmik, Sabyasachi Sengupta [Texas Instruments]
PaperPresentation

AMS
Reducing Library Design Effort with Cadabra Layout Automation
Author(s): Saroj Kumar Satapathy, Pappu Satyanarayana [LSI Corporation], Vishnu Kanchi [Synopsys]
PaperPresentation

Physical Design
Hierarchical Implementation of Cortex-A9 MPCore Multicore Processor with Galaxy Platform
Author(s): Saran Kumar Seethapathi, Arvind Kumar Sharma, Rahoul Varma [ARM], Subrata Sen [Synopsys]
PaperPresentation

Verification
SystemVerilog: From Device Modelling to Emulation
Author(s): Yogesh Mittal [TranSwitch Corporation]
PaperPresentation

Synthesis and Test
Register Cloning For Accelerated Design Closure
Author(s): Aditya Ramachandran [Open-Silicon]
PaperPresentation

IsraelReliable Frequency Prediction @ RTL Level in Deep Sub-Micron Processes
Author(s): Hatem Yazbek [Marvell]
PaperPresentation

San JoseMigrating a Large-Scale Vera Testbench Infrastructure to SystemC and SystemVerilog - Risk Mitigation and Value Creation Strategies
Author(s): Srinath Atluri, Nimalan Siva, Anant Sakharkar [Cisco Systems Inc.]
PaperPresentation

SingaporeAchieving Good Clock Skew and Inter-Clock Balancing Results Using ICC CTS Flow
Author(s): Teng, Siong Kiong, Lim, Mui Liang [Intel Corporation]
PaperPresentation
2nd Place - Best Paper
Boston		Reducing Failing Testcase Length: Mixing Brute-Force and Intelligence to Extract Meaningful Information from Many Simulations
Author(s): Jonathan Wolfe [MediaTek Wireless, Inc.]
PaperPresentation

EuropeSeamless Refinement from Transaction Level to RTL Using SystemVerilog Interfaces
Author(s): Jonathan Bromley [Doulos Ltd.]
PaperPresentation

San JoseAre We There Yet?
Author(s): Nancy Pratt [IBM], Dwight Eddy [Synopsys, Inc.]
PaperPresentation

SingaporeARM-based SoC Verification with SystemVerilog Functional Coverage
Author(s): Thia Chin Tong, Cheow Wai Meng, Tan Lay Hong [Solomon Systech Pte. Ltd.]
PaperPresentation
3rd Place - Best Paper
Boston		Just When You Thought It Was Safe to Start Coding Again... Return of the SystemVerilog Gotchas
Author(s): Shalom Bresticker [Intel Corporation]
PaperPresentation

EuropeEvaluation of Four Popular Fastmos Tools for Simulating DRAM Circuits
Author(s): Horst Fischer, Guoxing Zhang, Holger Günther [Qimonda AG]
PaperPresentation

San JoseOpenVera/RVM to SystemVerilog/VMM Conversion: How to Avoid 'Death By a Thousand Cuts'
Author(s): Venkata Chintapalli, Dan Steinberg [Integrated Device Technology]
PaperPresentation

SingaporeCost Effective Metal-mask ECO Flow
Author(s): Sudhakar Sayana [Infineon Technologies]
PaperPresentation
Best First-Time Presenter
Boston		Using Cosimulation of MATLAB and Simulink with VCS in a Functional Verification Environment
Author(s): Eric Cigan, David Lidrbauch [The MathWorks, Inc.]
PaperPresentation

EuropeModeling and Simulation of Multi Degree-of-Freedom Micro-Machined Accelerometer with Sigma-Delta Modulator
Author(s): Christopher J. Welham, Gunar Lorenz, Stephane Rouvillois [Coventor Sarl], Michael Kraft [Southhampton University], David King, David Combes, Mark McNie [QinetiQ]
PaperPresentation Video

San JoseMigrating a Large-Scale Vera Testbench Infrastructure to SystemC and SystemVerilog - Risk Mitigation and Value Creation Strategies
Author(s): Srinath Atluri, Nimalan Siva, Anant Sakharkar [Cisco Systems Inc.]
PaperPresentation
Technical Committee Award
Boston		Just When You Thought It Was Safe to Start Coding Again... Return of the SystemVerilog Gotchas
Author(s): Shalom Bresticker [Intel Corporation]
PaperPresentation

EuropeDesign For Test Insertion on a Very Complex VLSI Using Synopsys Galaxy Flow
Author(s): Cyrille Thomas [Bull SAS]
PaperPresentation

San JoseGetting Synchronous Resets Right!
Author(s): Noah Aklilu [Cisco Systems, Inc.], Anthony Redhead [XtremeEDA Corp.], Pervinder Trehan [Synopsys, Inc.]
PaperPresentation
Technical Committee Award Honorable Mention
Boston		DC Graphical: The Promise and the Reality
Author(s): Philip Watson [ARM, Ltd.], Tom Fairbairn [Synopsys, Inc.]
PaperPresentation

A Utility for Leakage Power Recovery within PrimeTime-SI
Author(s): Bruce Zahn [LSI Corporation]
PaperPresentation

EuropeAdvanced DFT Implementation Using SNPS DW Components and Galaxy Test
Author(s): Manu Baby, Vijay Sarathi [Dubai Circuit Design]
PaperPresentation

Transition Fault Test Pattern Generation Optimization using On-Chip PLL and Implication on Compression Techniques
Author(s): Frederic Hiebel [Texas Instruments Inc.]
PaperPresentation

San JoseUsing NanoTime for Custom Digital Macros
Author(s): Bingxiong Xu, Kevin Stiles [LSI Corp.], Cheung Lam, Louis Andrews [Synopsys]
PaperPresentation

Design for State Retention: Strategies and Case Studies
Author(s): David Flynn [ARM, Ltd], Alan Gibbons [Synopsys]
PaperPresentation


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