SNUG Boston 2010 Proceedings |
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| | User Papers and Presentations | | TA1 SystemVerilog and Verilog Preprocessor | Stick a Fork in It: Applications for SystemVerilog Dynamic Processes
Author(s): Doug Smith, David Long [Doulos] |
| The Verilog Preprocessor: Force for `Good and `Evil (3rd Place - Best Paper)
Author(s): Wilson Synder [Cavium Networks] |
| | TA2 VMM | Compressing and Simplifying Scoreboarding - Reducing the Redundancy of Multiple Scoreboards with the VMM Data-Stream Scoreboard
Author(s): James Keithan [Convergence Verification] |
| Customizing VMM Transactors with Options (Technical Committee Award Honorable Mention)
Author(s): Joe Manzella [LSI Corp.] |
| | TA5 Advanced FPGA Synthesis and P&R Techniques | Achieving Faster Turnaround Time and Better QOR using Compile Points and Design Preservation Flow for Virtex Devices (2nd Place - Best Paper, Best First-Time Presenter)
Author(s): Mike Spofford, Kate Kelly [Xilinx Inc.] |
| | TB2 VMM, UVM and ATPG | Optimized ATPG Patterns: The Lowest Power For Your Buck
Author(s): Eric Pavao, Joe O'Neill, Michael Graham [Analog Devices, Inc.], Lori Schramm [Synopsys, Inc.] |
| Re-Using a SystemVerilog/VMM/RAL Environment in Analog/Digital co-simulation
Author(s): James Lee, Ashley Winn [Analog Devices, Inc.] |
| | TB3 Discovery AMS, XA and Custom Designer | Analog & Mixed Signal Verification of Data Conversion Systems using XA & XA-VCS-MX
Author(s): Alan Morton, Yuval Shay [STMicroelectronics, Inc.], Minh Tran [Synopsys, Inc.] |
| Deployment of Custom Designer in 40nm
Author(s): Michael Wagner [Lantiq GmbH], Oliver Baer [Synopsys GmbH] |
| Real Behavioral Models for System/Verilog/A/AMS
Author(s): Bill Ellersick [Analog Circuit WorksTM, Inc.] |
| | TB4 Reusable UPF, DC and Efficient Timing Closure | Reusable UPF for Multi-Voltage Design & Handling Analog Macros in Power Subsystem
Author(s): Krishna Vitalla [Microchip Technology Inc.] |
| | TB5 FPGA Constraints, Embedded Processors in FPGA, IC Security | Stealth Towards Clone Wars
Author(s): Kumar N. Dwarakanath, Paul Bradley [Tiger's Lair Inc.] |
| | TB6 PT ECO, Web-Based Reporting and PTPX | A Flexible and Portable Static Timing Environment Using PrimeTime and Web-based Reporting
Author(s): Terry Biggs , Steven Woodward [ON Semiconductor] |
| Experiences with PrimeTime ECO capabilities (1st Place - Best Paper)
Author(s): Bruce Zahn [LSI Corp.] |
| Measuring Active Power A User Perspective
Author(s): Duane Galbi, Karthik Kannan [Intel Corp.} |
| | TC1 LEDA/MVSIM and Addressing Verification Challenges | Power Intent Specification Creation and Verification for Multi-Rail Cells using LEDA/MVSIM
Author(s): Anil Deshpande, Ramanan Balakrishnan [Advanced Micro Devices], Viswanath Sundaraman, Vikram Malik, Tushar Parikh [Synopsys, Inc.] |
| | Tutorials | | TA3 HSPICE and AMS Verification | HSPICE Signal Integrity Topics: Checking S-Parameter Data and Introducing IBIS-AMI Support
Author(s): Dave Chou [Synopsys Inc.] |
| | TA4 The Evolution of Synthesis and Place & Route and New Features in 2010.03 DC/ICC | Galaxy Update - Design Compiler and IC Compiler 2010.03 Highlights
Author(s): Chris Puff, Steve Danielson [Synopsys, Inc.] |
| | TA5 Advanced FPGA Synthesis and P&R Techniques | Advanced Use of TCL Language to Increase Productivity, Debug and Analysis of Synplify FPGA Based Projects
Author(s): Carl Cleaver [Synopsys, Inc.] |
| | TA6 PrimeTime Updates and Multicore Analysis | PrimeTime Multicore Analysis
Author(s): Pete Jarvis [Synopsys, Inc.] |
| What's New in PrimeTime 2010.06
Author(s): Danny Rawlings [Synopsys, Inc.] |
| | TB1 VCS 2010.06 Update | VCS 2010.06 Update
Author(s): John Girard, Dharmesh Shah, Alex Wakefield [Synopsys, Inc.] |
| | TB2 VMM, UVM and ATPG | Verification Methodology, Are We Really Rolling the Dice?
Author(s): Chris Thompson [Synopsys, Inc] |
| | TB4 Reusable UPF, DC and Efficient Timing Closure | Feasability for IC Implementation
Author(s): Barry Turner [Synopsys, Inc.] |
| You Don’t Make Timing in Design Compiler, Now What?
Author(s): Craig Maiman [Synopsys, Inc.] |
| | TB5 FPGA Constraints, Embedded Processors in FPGA, IC Security | FPGA Prototyping of Embedded Processors
Author(s): Peter Calabrese [Synopsys, Inc.] |
| Translating FPGA Vendor Constraint into Synplify SDC format
Author(s): Sara Steigerwald [Synopsys, Inc.] |
| | TC2 ATPB | Optimizing Compression and ATPG using Synopsys 2010.03
Author(s): Adam Cron [Synopsys, Inc.] |
| | TC3 Custom Designer | Synopsys Custom Design Solution featuring Custom Designer Demo
Author(s): Fredrik Ivarsson [Synopsys, Inc.] |
| | TC4 IC Compiler & In-Design Physical Verification | In-Design Physical Verification for Faster Time to Tapeout
Author(s): Dan Marolda [Synopsys, Inc.] |
| | TC5 Cloud Computing | From EDA Infrastructure to Cloud Computing
Author(s): Glenn Newell, John Mincarelli [Synopsys, Inc.] |
| | TC6 Galaxy Constraints Analyzer & Lynx | Galaxy Constraints Analyzer: Constraints Debugging Made Easy
Author(s): Mark DiGiovanni [Synopsys, Inc.] |
| Increased Productivity and Higher Predictability with the Lynx Design System
Author(s): Adam Bush [Synopsys, Inc.] |
| | Vision Session | | TA3 HSPICE and AMS Verification | The Future of AMS Verification
Author(s): Warren Wong [Synopsys, Inc.] |
| | TA4 The Evolution of Synthesis and Place & Route and New Features in 2010.03 DC/ICC | Logic Synthesis and Place & Route | New Links in a Long Standing Partnership
Author(s): Antun Domic [Synopsys, Inc.] |
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