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| User Papers and Presentations |
| MA1 - Constrained Random, Functional Coverage and Verification Techniques |
A SystemVerilog Coverage Driven Test Generator for Processor Design Verification (Technical Committee Award Honorable Mention)
Author(s): David Brownell, Tushar Ringe [Analog Devices] |
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Advanced Random Constraints to Manage the Data Flow of a Packet Memory
Author(s): John Stiles [Silicon Logic Engineering, Inc.] |
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Customizing VMM to Add Global Progress Management
Author(s): Boone Severson, John Thompson [Cray Inc.], Tyler Bennett [Synopsys, Inc.] |
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| MA2 - Synthesis Strategies and Evaluation of DC-Topographical |
Evaluating the Benefit of DC Topographical to the Entire Design Flow
Author(s): Shane Keating, David Lamb [Analog Devices], John Geremia [Synopsys, Inc.] |
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Evaluation of DC-Topographical
Author(s): Branimir Malnar, Santana Lewis, Goran Zelic, Raghu Raman [Intel Corp.], Craig Maiman [Synopsys, Inc.] |
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Winner-Take-All Optimization for Design Synthesis
Author(s): Kapil Gaba [Agere Systems], Christopher Rose [Synopsys, Inc.] |
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| MA3 - ICC Success Stories |
Breaking the Gigahertz Speed Barrier with an Automated Flow Using Commercial Standard Cell Libraries and Memories
Author(s): Soumya Banerjee, Avishek Panigrahi [MIPS Technologies], Dan Lefrancois, Sharrone Smith [Synopsys, Inc.] |
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Success with MCMM
Author(s): Jeff Shi [LSI Corp.], Sohail Siddiqui [Synopsys, Inc.] |
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| MA4 - Static Timing for Post-layout and Custom Circuits |
Bottoms-Up Hierarchical Timing Budgeting using PrimeTime
Author(s): Duane Galbi, Ranjit Loboprabhu, Christopher McGlone [Intel Corp.] |
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Hold Me Please! How to Fix Post-Route Hold Violations Quickly and Easily Using Distributed Multi-Scenario Analysis
Author(s): Dwight Galbi [Analog Devices, Inc.], Beth Herman, Brandon Waldo, Mike Castellano, Chris Papademetrious [Synopsys, Inc.] |
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Static Timing Analysis on Custom Circuits at the 65nm Technology Node and Beyond, Can NanoTime Cut You Some Slack?
Author(s): Lakshmikant Mamileti [Qualcomm], Patrick Donahue [Synopsys, Inc.] |
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| MA5 - Analog Mixed Signal |
Efficient Full-Chip Verification of STMicroelectronics Smart Power Applications with HSIM-NCSim Co-Simulation Methodology
Author(s): Branimir Ivetic, Claudio Vignati, Lyes Djama [STMicroelectronics], Carlo Borromeo [Synopsys, Inc.] |
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Multi-Gigabit Serial Link Analysis - Piecing Together a Design and Verification Strategy
Author(s): Michael Steinberger, Todd Westerhoff [SiSoft] |
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| MB1 - Verification Using VMM Methodologies and Techniques |
A VMM Based Generic Interrupt Handling Mechanism
Author(s): Ning Guo, Rich Musacchio, Steve D'onofrio, Ambar Sarkar [Paradigm Works] |
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Creating Stimulus and Stimulating Creativity: Using the VMM Scenario Generator (2nd Place - Best Paper)
Author(s): Jonathan Bromley [Doulos Ltd.] |
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| MB3 - Final Physical Finishing |
From Validation to Generation: Making Hercules do the Heavy Lifting (Best First-Time Presenter)
Author(s): Dale Donchin [Analog Devices, Inc.] |
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Multiphase Flow for Meeting Metal Density and Gradient Requirements at 65nm
Author(s): Jim Dodrill, Dwight Galbi [Analog Devices, Inc.], Moheb Basta, Mike Castellano [Synopsys, Inc.] |
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| TA1 - Design & Debug using SystemVerilog |
Finding A Tricky IP Bug With SVA (A Real World Example)
Author(s): Paul McGaugh [Broad Reach Engineering, Inc.], David Castle [Synopsys, Inc.] |
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SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification (1st Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.] |
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| TA2 - DFT Techniques for Yield Enhancement |
Failure Data Gathering and Analysis for Yield Enhancements of a COT Manufacturer
Author(s): Zahi Abuhamdeh, Vincent D'Alessandro, Bob Hannagan [TranSwitch], David Chagnon [Synopsys, Inc.] |
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Power Management During Test on the ARM Cortex-A8 Microprocessor
Author(s): Teresa L McLaurin [ARM Inc.], Glenn Boyer, Lori Schramm, Don Skinner [Synopsys, Inc.] |
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| TA3 - Floorplan Challenges |
Highly Rectilinear Digital Place and Route Challenges Solved by Astro
Author(s): Eric Ryherd [Cypress Semiconductor] |
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Honey, I Shrunk the Die. Don't Worry, the Kids are OK.
Author(s): Jonathan Bahl [COT Consulting, Inc.] |
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When Floorplans Attack: How To Balance Routing, Timing and Area on Problematic Designs (Technical Committee Award)
Author(s): John Vargas [Unisys], Peter Jarvis [Synopsys, Inc.] |
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| TA4 - Low Power Prediction and Implementation |
Advanced Low Power, Multi-Supply Implementation Techniques for 65nm and Beyond using DCT and ICC
Author(s): Dwight Galbi [Analog Devices], Brandon T Waldo [Synopsys, Inc.] |
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Complex Rectilinear Floorplan and Implementation for Multi-Voltage Domain, Low Power ASICs
Author(s): Govindarajan Natarajan, Shankar NG, Ramakrishna Alluri, Venkateswra Rao Arumilli, Zameer Ahmed, Seshagiri TN, Neel Das [Tallika Corp.] |
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Moving to the "Next" Technology Node
Author(s): Jim Vanaria, Paul Pua [TranSwitch Corp.] |
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| TA5 - System-Level SOC Validation |
The Diagnostic Channel: Increasing Visibility and Control in SystemC Models
Author(s): Joseph Chapman [The MITRE Corp.] |
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Using SystemVerilog DPI to Create Comprehensive Hardware/Software Co-Verification Environments
Author(s): Alicia Strang, Pei-hsiu Suen [Marvell Semiconductor, Inc.] |
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| TB4 - IR Drop |
Full Chip IR Drop Methodology for Low Power Applications
Author(s): Shailja Garg, Sanjay K Sancheti, Anup Nayak [Cypress Semiconductor] |
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IR Drop Analysis of a 65nm Complex Power-Gating Design: Issues and Solutions
Author(s): Michael Allen, Dwight Galbi, Joe Geisler [Analog Devices], Kaijian Shi, Julio C Hernandez [Synopsys, Inc. ] |
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| TB5 - Tips to Integrate and Verify Reusable IP |
The Ten Edits I Make Against Most IP (3rd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Wilson Snyder [SiCortex, Inc.] |