Conference at a Glance    

SNUG France | 14 June, 2012 
Grenoble World Trade Center
Place Robert Schuman
38025 Grenoble Cedex 1

 Time

 Description

8:30-9:30
Registration & Breakfast
9:30-10:30
Welcome and Keynote
Joachim Kunkel, Sr. Vice President and General Manager, Synopsys Solutions Group
Video Message from Aart De Geus, Synopsys CEO & Chairman of the Board
10:30-10:45
Break
Front-end Implementation and IP
Digital Verification
Physical Design
and Sign-off
Design for Test
FPGA and System
AMS Design and Verification
10:45-12:15A1 User Session
Front-to-Back Implementation
A2 User Session
Low-Power Verification
A3 User & Tutorial Session
Hierarchical Design & Floorplanning
A4 User Session
Design for Test and ATPG I
A5 User & Tutorial Session
FPGA Implementation
A6 User Session
AMS Verification and Sign-Off
12:15-13:30
Lunch
13:30-15:00B1 Tutorial  & Demo Session
Front-End IP Integration
B2 User & Tutorial Session
Testbench and verification IP
B3 User & Combo Session
Clock Tree Synthesis & Sign-Off
B4 User & Tutorial Session
Design for Test and ATPG II
B5 User &
Tutorial Session

Advanced FPGA Design Techniques
B6 User & Tutorial/ Demo Session
Digital/Analog Co-design
15:00-15:30
Break
15:30-17:00C1 User & Tutorial Session
RTL Synthesis
C2 Combo and Tutorial Session
Core Simulation
C3 User & Tutorial Session
Design Closure
C4 User, Tutorial and R&D Session Advanced Test TechniquesC5 Tutorial & Demo Session
Custom Processors & Design Verification using FPGA
C6 Tutorial Session
Analog IPs & Circuit Simulation
17:00-18:00
Awards and Refreshments