| Time | Description |
| 8:00-9:00 | Registration and Breakfast |
| 9:00-10:15 | Welcome & Keynote: Jeff Johnson, Sr. Director, Application Consulting - Synopsys, Inc.
Keynote Address: Aart de Geus, Chairman of the Board and co-CEO - Synopsys, Inc. |
| 10:15-10:30 | Break |
| | Front-End Implementation | Physical Implementation | Verification |
| 10:30-12:30 | FA1 User and Tutorial Session:
Physical Synthesis, PrimeTime Performance, and Constraints Analysis
| FA2 User and Tutorial Session:
Cortex-A15 Best Practices and Structured Design | FA3 User and Tutorial Session:
Simulation Performance, Verification IP and X-Optimism |
| 12:30-1:30 | Lunch and Executive Address: Ty Garibay, VP of Engineering - Altera |
| 1:30-3:00 | FB1 User and Tutorial Session:
Leakage Reduction and Processor Design | FB2 User and Tutorial Session:
Cortex-A15 Best Practices and 20nm Design | FB3 User and Tutorial Session:
Low power Verification, X-Propagation and Testbench Timing |
| 3:00-3:15 | Break |
| 3:15-5:15 | FC1 User and Tutorial Session:
Test Methodology | FC2 User and Tutorial Session:
ICC Design Flows and Integrity EM/IR Analysis | FC3 User and Tutorial Session:
Covergroups, Functional Coverage and Low Power Verification |
| 5:00-7:00 | Sponsor Expo and Awards Presentation |