|Addressing 16nm FinFET Challenges to Tapeout a 50M+ ARM® Cortex®-A57 processor-based SoC using Synopsys IC Compiler™|
In this video, you’ll hear briefly about Synopsys’ participation at ARM TechCon 2014 followed by a Synopsys and HiSilicon joint presentation on HiSilicon's successful tapeout of their first production SoC in 16nm FinFET technology.
Kelvin Chen, Principle Engineer, COT Department, HiSilicon
Muming Tang, Staff Applications Consultant, Synopsys
|Tapeout of a High-Performance ARM Cortex-A57 Processor-Based Server SoC Using Synopsys Galaxy Design Platform|
In this video, you’ll hear briefly about Synopsys’ participation at ARM TechCon 2014 followed by AMD’’s presentation on the recent tapeout of the AMD OpteronTM A1100 “Seattle” SoC based on ARM's 64-bit ARMv8 architecture.
Manoj Rehani, Director, ASIC Design, AMD
Phillip Young, Principle Member Technical Staff, ASIC Design, AMD
|Efficient Hardening of ARM Cortex-A57/-A53 Processor Subsystems in FD-SOI Process Technology Using Galaxy Design Platform|
In this video, you’ll hear briefly about Synopsys’ participation at ARM TechCon followed by STMicroelectronics sharing its approach to the efficient implementation of ARM® Cortex®-A57/-A53 processor-based system-on-a-chip (SoC) designs.
Arnaud Rayer, Senior Staff Backend Engineer, STMicroelectronics
|A Simple Formula for Success with Next-Generation Wearables to High-Performance |
Through relentless collaboration efforts in all aspects of the design cycle, key ecosystem partners - Samsung Foundry, Synopsys and ARM - have made it easier for leading customers to achieve first-time-silicon success with their leading-edge 28nm and 14nm SoC designs. With this continued commitment to reducing risk and minimizing the design cycles, these three companies are bringing differentiated solutions to customers, including silicon-proven PDKs, foundation IPs, advanced IPs and design flows.
Rob Aitken, ARM; Glenn Dukes, Synopsys; Kelvin Low, Samsung SSI; Phil Dworsky, Synopsys
|Energy Efficient Implementation of ARM® Cortex™-A57/-A53 Processor Cores in FD-SOI Process Technology|
STMicroelectronics shares its approach to delivering optimized energy efficient solutions for the SoC market. Highlights from the low power implementation and verification methodology developed with Synopsys.
Senior Principal Engineer, Design & Architecture for Energy ,Efficiency CPU & GPU subsystems
|Implementation and Virtual Prototyping of a 2.6 GHz ARM® Cortex®-A15 in a big.LITTLE SoC |
Fujitsu Semiconductor provides an overview of the Galaxy Implementation technologies used on the Cortex-A15 processor tapeout and the use of Synopsys Virtualizer™ Development Kit (VDK) to accelerate software development.
Seiji Goto, Manager, Imaging Solution Division, Advanced Products Business Unit,
Fujitsu Semiconductor Limited
|Optimizing Implementation of ARM Processor Cores with the Galaxy Platform in advanced TSMC Processes|
Synopsys, ARM and TSMC hosted a session that highlighted the latest technologies including: Reference Implementations to optimize processor core implementation, trade-offs and best practices utilized to implement an ARM® Cortex®-A15 dual-core processorand a Cortex-A7 quad-core processor, collaboration to optimize ARM Mali™ T600 family GPUs in the TSMC 20SOC process, and design enablement for the TSMC 16nm FinFET process.
Willy Chen, TSMC; Bernard Ortiz de Montellano, ARM; Joe Walston, Synopsys; Tim Whitfield, ARM Taiwan Ltd.
|Reference Implementation Collaboration for Optimized Cortex-A15 and Cortex-A7 Processor Introduction |
Introducing the ARM-Synopsys optimized reference implementations of the ARM Cortex™-A15, Cortex-A7 processors, and CoreLink™ CCI-400 interconnect for the Galaxy Implementation Platform using ARM Artisan physical IP in TSMC 28HPM process technology.
Bernard Ortiz de Montellano, Product Manager, ARM Processor Division, Phil Dworsky, Director, Strategic Alliances, Synopsys
|Collaboration to Enable Design Flows with ARM Artisan Physical IP in Advanced Process Technologies - Introduction|
Introducing the ARM-Synopsys collaboration to enable advanced process design flows with the Galaxy implementation tools through Artisan physical IP. John introduces early 3-way collaboration between ARM, Synopsys and TSMC on 16nm design enablement.
John Heinlein, Vice President, Marketing, Physical IP Division, ARM, Phil Dworsky, Director, Strategic Alliances, Synopsys
|20nm Flow Development and Optimized Mali GPU Implementation Introduction |
Introducing the ARM-Synopsys collaboration to smooth and optimize the design flow with the Galaxy Implementation Platform and ARM Artisan Physical IP in TSMC 20nm SoC process technology.
Tim Whitfield, Hsinchu Design Center Manager, ARM, Phil Dworsky, Director, Strategic Alliances, Synopsys
|Demonstrating the 20nm Implementation Ecosystem using an ARM Mali GPU with a Full Galaxy Tool Flow|
Several Synopsys customers presented at DAC 2013 their lasts collaborations using the Galaxy Implementation Platform. ARM presented how they optimized the Galaxy design flow with ARM Artisan Physical IP in TSMC 20nm SoC process technology.
Tim Whitfield, Hsinchu Design Center Manager, ARM + others
|ARM-Synopsys Verification collaboration to enable ARM-based SoCs|
Industry leaders, such as Altera, ARM, Freescale, Qualcomm and STMicroelectronics shared their views on what's driving SoC complexity and how their teams have achieved success at DAC 2013.
Paul Matin, Senior Product Manager, ARM
|Memory Simulation in a FinFET World - Overcoming Challenges Introduction|
George Lattimore and Ron Moore, Director discuss the challenges of modeling embedded memories in FinFET process technologies and how ARM and Synopsys collaborated to address these challenges using Synopsys FineSim.
George Lattimore, Director of Engineering, ARM
Ron Moore, Director, Strategic Accounts, ARM
Phil Dworsky, Director, Strategic Alliances, Synopsys
|Overcoming challenges of FinFET memory IP using FineSim|
Synopsys hosted an AMS Luncheon at DAC 2013. At this event, ARM presented the challenges of modeling embedded memories in FinFET process technologies and how ARM and Synopsys collaborated to address these challenges using Synopsys FineSim.
George Lattimore, Director of Engineering, ARM
|Optimized Implementation Of A Gigahertz+ ARM® Cortex™-A15 Processor |
Synopsys Galaxy™ Implementation Platform was used for a low power implementation of an ARM® Cortex™-A15 processor for mobile apps. Key techniques were used to achieve a 20% improvement over traditional implementation techniques.
Brian Millar, Physical Implementation Lead, High Performance CPU Team, Samsung
|Achieve Gigahertz+ Performance on ARM® Cortex©-A15 Processor Implementation |
Synopsys presented its high performance core methodology, highlighting key technologies to achieve challenging performance/power targets. HiSilicon shared its experiences and results on the successful tapeout of a complex ARM Cortex-A15 based SoC design.
Kevin Yip, Senior Applications Consulting (AC) Manager, Synopsys.
Catherine Xiayu, Director of the COT Design Department, HiSilicon
Chunsheng Liu, Principle Engineer in the COT Design Department, HiSilicon.
|High-Performance Physical Design of a 28nm Quad-Core ARM® Cortex™-A15 Processor|
Highlights the Synopsys IC Compiler™ flow for a 28nm quad-core ARM® Cortex™-A15 processor. Various physical design techniques were used to obtain very high clock frequencies which can be applied to ARM and other 28nm high-performance chips.
Jason Karka, Designer, Texas Instruments
Michael Robinson, Designer, Texas Instruments
|SNUG Silicon Valley Keynote: Partnering for Low Power|
This presentation from SNUG 2012 describes work ARM is doing in physical IP, interconnect, and processor sub-systems to enable energy efficient systems. It will also discuss the importance of system profiling and analysis, and definition of new industry.
John Cornish, Executive Vice President ARM, Ltd.