System-Level Catalyst Member 

Structured Design Verification (SDV) 

SDV Logo Successful integration of RTL blocks into system level models depends on accurate, consistent adapters. The Synopsys System-Level Catalyst program enables SDV to deliver consistent support for the Synopsys Virtualizer platform across a variety of co-simulation & co-emulation environments with its combination of auto-generated standard IP, services for custom protocol transactors and customer-enabling TransactorWizard toolset.

- Bernard Deadman, CEO of SDV Ltd


Product Description
Transaction-level testbench development enables users to focus on scenarios, creating better test cases with less effort. Re-useable transactors translate between transaction-level records and protocol-compliant interface signals, and detect protocol violations. SDV’s formally-based transactor generation technology creates optimal support from system level to RTL simulation from the same protocol description and automatically creates functional coverage and transaction-recording features.

SDV provides flexible support for verification methodologies with the TrasactorWizard interface generation tools, ready-to-run transaction interfaces, configurable simulation source code for license-free runtime interfaces, configurable protocol descriptions and full implementation, generation & validation services.

Interoperability Description and Customer Benefit
SDV’s re-useable transactors translate between transaction-level records and protocol-compliant interface signals, and detect protocol violations. Together with Synopsys Virtualizer and DesignWare System-Level Library they allow users to reuse high-level models for RTL verification and software development using hybrids of FPGA prototyping and virtual platforms.

Tell me more about SDV and Virtualizer, System-Level Library.

Flow Diagram

Flow Diagram