| System-level design has become quite complex. Time-to-market pressures, multiple dimensions of design tradeoffs, and issues in quality, safety, and reliability all factor in, as well as overall cost. SysML-based methodologies are emerging as the preferred choice for high-level system description and collaboration in the System Engineering domain. In addition, the Electronic Design community is coalescing around SystemC and TLM 2.0 to raise the abstraction level. It is therefore critical and natural to leverage SysML model artifacts further down in the flow, including hardware design, verification, and implementation. MetaSyn’s SysML-to-SystemC synthesis technology bridges the gap between these tool chains through automated synthesis of SystemC models from SysML. ExperMeta is pleased to be working in cooperation with Synopsys to create an automated and unified flow between the System Engineering domain and Synopsys Virtual Prototyping Solutions. |
- Sandeep Desai, Co-Founder of ExperMeta
MetaSyn from ExperMeta provides SysML-to-SystemC synthesis technology that bridges the automation gap between System Engineering model artifacts and traditional Electronic Design tool chains. Structure, interfaces, behavior, and timing are represented at the user’s choice of abstraction level, including:
- Transaction Level based on TLM 2.0 (Loosely Timed or Approximately Timed)
- Cycle Accurate
- SystemC synthesizable subset
Interoperability Description and Customer Benefit:
MetaSyn enables users of Synopsys Virtual Prototyping Solutions to easily integrate System Engineering models into their virtual platform environment. Leveraging of specification-based executable SysML models in combined HW/SW simulations enables early system design analysis, and provides executable system models for early software development.
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