Synopsys EDA Interoperability Forum  

24th Synopsys EDA Interoperability Forum     

Yatin Trivedi and Rich Goldman provide a recap of the 2011 Forum

The EDA Interoperability Forum provides EDA vendors and customers an opportunity to exchange information and ideas on EDA tool interoperability. The Forum features contemporary topics of interest and controversy that are relevant to design engineers, EDA vendors, and IP providers. Topics include information on new interface technologies, future enhancements, upcoming news, and successes from developers and customers. The Forum continues to be the premier industry event to cover a wide variety of standards and organizations, addressing challenges and solutions in the electronic design standards arena.

The 24th EDA Interoperability Forum – November 2011

At this year’s forum, several of our keynote speakers from over the years joined us to discuss important interoperability issues and share their visions for how we can tackle the challenges and opportunities ahead. The presentations from the event are now available for viewing and PDF download.

Rich GoldmanRich Goldman
Vice President, Corporate Marketing and Strategic Alliances, Synopsys

Welcome Video | PDF

Rich Goldman is the Vice President of Corporate Marketing and Strategic Alliances for Synopsys and CEO of Synopsys Armenia, which the National Assembly of The Republic of Armenia recently proclaimed the best company in the country. His current responsibilities include Marketing Communications, Public Relations, Events, Creative Services, Web, Market Research, Executive Speaking placement and preparation, Community and Employee Communications, Strategic Alliances, University Programs, Standards, and Industry Relations.

Rich earned a BSCS from Syracuse University, an MBA and MS Engineering Management from The University of Dallas, and an honorary Doctorate from The State Engineering University of Armenia.

Aart de GeusAart de Geus
Chairman and CEO, Synopsys

Welcome Video | Closing Video

Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a start-up synthesis enterprise to a world leader in electronic design automation (EDA). With 25 published papers and numerous industry honors, Aart has long been considered one of the world's leading experts on logic simulation and logic synthesis.

Among the prestigious technology awards that Dr. de Geus has received is the honor of being named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999. He was honored for pioneering the commercial logic synthesis market with the IEEE Circuits and Systems Society Industrial Pioneer Award in 2001, as well as for his "contributions to, and leadership in, the technology and business development of Electronic Design Automation" with the 2007 IEEE Robert N. Noyce Medal. In 2002, shortly after transacting the largest merger in EDA history, Dr. de Geus was named CEO of the Year by Electronic Business magazine. In November 2005, Electronic Business magazine selected Dr. de Geus as one of "The 10 Most Influential Executives." In November of 2007, he was awarded the Silicon Valley Leadership Group (SVLG) "Spirit of the Valley" Lifetime Achievement Award. In October 2008, he was presented with the Phil Kaufman Award for distinguished contributions to EDA. And in December, 2009, he was awarded the GSA "Morris Chang Exemplary Leadership Award."

Dr. de Geus is active in the business community as a member of TechNet, as well as serving on the Boards of the Silicon Valley Leadership Group (SVLG), Applied Materials, the Global Semiconductor Alliance (GSA), and the Electronic Design Automation Consortium (EDAC).

Philippe MagarshackPhilippe Magarshack
Technology R&D Group VP, STMicroelectronics

EDA Standards over the Past 10 Years: The View from SoC Designers
Video | PDF

Philippe Magarshack graduated with an engineering degree from Ecole Polytechnique, France in 1983. He designed arithmetic units for AT&T's 32b Processor Family at AT&T Bell Labs until 1989, in New-Jersey, Pennsylvania and California. He then joined Thomson-CSF as manager of their military ASIC Design Solution in Grenoble France.

In 1995, he joined STMicroelectronics' Central R&D Group to manage advanced CMOS design platforms in Crolles, France.

Magarshack now manages ST's Central CAD Group, delivering Design Solutions to all ST Product Groups in Consumer, Automotive, Telecom and Computer Peripherals, in Nodes from 350nm to 20nm. Magarshack oversees ST's CAD Vendor strategy and represents ST at the SI2 Board and at ISDA.

Jim HoganJim Hogan
Private Investor

The Sequel: A Fistful of Dollars
Video | PDF

Jim Hogan has over 35 years experience in the semiconductor design and manufacturing industry. He is currently the managing partner of Vista Ventures, LLC.

Jim was a general partner at Telos Venture Partners and senior vice president of business development at Artisan Components Inc., now part of ARM Holdings PLC. He held senior engineering, marketing and operational management positions at Cadence Design Systems, Inc., National Semiconductor Corporation and Phillips Semiconductor. He was also Chief Operating Officer of Smart Machines, Inc., a semiconductor equipment automation company.

Hogan holds a B.A degree in mathematics, a B.S. degree in computer science and an M.B.A all from San Jose State University. He serves on the Board of Advisors at San Jose State's School of Engineering, and on several private companies' board of directors. Additionally Jim serves as a strategic advisor to several public technology companies.

Mark TempletonMark Templeton
President, Scientific Ventures, LLC

Survival of the Fittest and the DNA of Interoperability
Video | PDF

Mark Templeton is the president of Scientific Ventures, an investment firm working with entrepreneurs to re-invent the way that we live through the application of science and technology.

From 1991 to 2004, Mark was a co-founder and the chief executive officer of Artisan Components, a leading semiconductor intellectual property company. In 2004, Artisan Components was acquired by ARM Holdings. Following the acquisition of Artisan, Mark served as president of ARM Holdings North America and as ARM’s chief strategy officer and was a member of the ARM Holdings board of directors.

Mark currently serves on the boards of several U.S. and China based technology companies. Mark holds a B.S. in Engineering from Boston University.

Michael KeatingMichael Keating
Synopsys Fellow (retired)

Low Power Update: Treading Water in a Rising Flood
Video | PDF

Mike Keating is a Synopsys Fellow (retired). In his 14 years at Synopsys, he focused on IP development methodology, hardware and software design quality and low power design. His most recent research focuses on high level design and the challenges of designing extremely complex systems.

Mike received his BSEE and MSEE from Stanford University, and has over 25 years experience in ASIC and system design. He is co-author of the Reuse Methodology Manual and the Low Power Methodology Manual. He is the author of the recently published The Simple Art of SoC Design.

At ISQED In 2007 Mike received the Quality Award for contributions to quality in electronic design.

Shay Gal-OnShay Gal-On
Dir. of Software Engineering, EEMBC

Multicore Technology: To Infinity and Beyond in Complexity
Video | PDF

Shay Gal-On is EEMBC's Director of Software Engineering and leader of the EEMBC Technology Center. At EEMBC, Shay created the EnergyBench and MultiBench Standards for benchmarking.

Prior to EEMBC Shay was Principal Performance Analyst in the Microprocessor Products Group at PMC Sierra where he influenced the design of new processors, including instruction set design, and optimized both hardware and software products. Other roles in the microprocessor industry over the past decade include at Improv Systems where Shay created unique hardware-software codesign tools, and at Intel where he created production libraries for analysis and optimization of binaries used in simulators, compilers, and binary translators.

Shishpal Rawat
Chair, Accellera

Evolution of Standards Organizations: 2025 and Beyond
Video | PDF

Shishpal Rawat is Director of Business Enablement Programs in TMG's Design Technology Solutions Group at Intel. For Intel’s Design Technology Group he manages strategic investments in EDA start ups, academic research and EDA standards. Shishpal has been at Intel for 23 years and has held a variety of Design and CAD management positions.

He served as Chair for Design Science Technical Advisory Board of the Semiconductor Research Corporation in 1998 and as Chair for the Integrated Circuit and Systems Sciences Technical Advisory Board in 1999. He served as an Associate Editor of ACM's Transactions on Design Automation of Electronic Systems from 2002 - 2005. He currently serves as the Chair of Accellera's board of directors and is also the Intel Capital observer on the boards of Coventor and Tela Innovations.

Shishpal earned M.S. and Ph. D. degrees in Computer Science from Pennsylvania State University, University Park, in 1982 and 1988, respectively and a B. Tech. degree in Electrical Engineering from Indian Institute of Technology, Kanpur, India, in 1979.

Past Interoperability Forum Presentations

October 2010
November 2009
November 2008
October 2007
April 2007
November 2006
May 2006
November 2005
April 2005
October 2004
April 2004
October 2003
April 2003