EDA Interoperability Developers' Forum Archive 

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General Session

• Welcome
  Rich Goldman, Synopsys
• From DFII to OpenAccess
  Joe Puchta, Silicon Canvas
• Interoperability Update
  Pamela McDaniel, Synopsys
• MAP-in Program Update
  Mark Lefevre, Synopsys
• OASIS Update
  Fabio Angelillis, Synopsys
• OpenMAST
  Chuck McIntyre, Synopsys
• SPIRIT Consortium
  John Swanson, Synopsys
• The Next Major Advance in Chip-Level Design Productivity
  Prof. A. Richard Newton, UC Berkeley
• IEEE SystemVerilog Update
  Oz Levia, Synopsys
• OpenKit "OK" Initiative
  Nick English, Accellera
• IP Interoperability: ARM's AMBA 3 Interface Family Enabling Advanced SoC Design
  Peter Aldworth, ARM
• EDAC O.S. Roadmap
  Pamela Parrish, EDA Consortium
• Liberty Delay Calculation Advancements
  Bill Mullen, Synopsys

SystemVerilog Forum

• Welcome
  Pamela McDaniel, Synopsys
• SystemVerilog Testbench Update
  Alex Wakefield, Synopsys
• User's Perspective on SystemVerilog
  Neil Korpusik, Sun Microsystems
• Exploiting SystemVerilog Testbench Support in ModelSim
  Dennis Brophy, MTI
• Synopsys SystemVerilog Support
  Tom Borgstrom, Synopsys
• FinSim’s Support of SystemVerilog
  Alec Stanculescu, Fintronic USA
• Closing Remarks and Raffle
  Rich Goldman, Synopsys

Low Power Forum

• The Elements of the Most Energy Efficient SoC Design
  Sun Microsystems
• Intelligent Energy Manager
  Clive Watts, Synopsys and David Flynn, Synopsys
• Design for Low Power
  Barry Pangrle, Ph.D., Synopsys
• PowerWise™ Technology
  Gordon Mortenson, National Semiconductor
• Silicon IP for Low Power Design
  Rob Aitken, Artisan
• Closing Remarks
  Rich Goldman, Synopsys